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spi: Fixes for v5.5
A small collection of fixes here, one to make the newly added PTP timestamping code more accurate, a few driver fixes and a fix for the core DT binding to document the fact that we support eight wire buses. -----BEGIN PGP SIGNATURE----- iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl4TMdwTHGJyb29uaWVA a2VybmVsLm9yZwAKCRAk1otyXVSH0M5UB/9w0mzrmuaJzctm3Jm8LiCIjJoZ0woQ chgbhm2C/I6idENxdUhaJ1YZMI6NkmJKpJy5tQ/QH4MnbOVT/vHIEmIsRYO0vYoF ApERJLia8da1OpiJlPTbsg3eUXVNmPMVeAkq5MgKSflaIjV6Ejc0FRWmgDYvzhu9 xkCsptAF7MYPUuHdBcjXPscSf1/w+FdDy8VYncEluyJ0NpGDU64N/XdTwRmsG8QW BxA1jPPKi445NsC+OV8SFfNZbeEXG2iSEBPvp4tMGtd0TiIp3UNLTRzMstEFE6SD hCzL9fQEzUgHD+B0vLmccyy0HR0phk6813jf9KeToAjAxKtf5XhQajW+ =Ad4n -----END PGP SIGNATURE----- Merge tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small collection of fixes here, one to make the newly added PTP timestamping code more accurate, a few driver fixes and a fix for the core DT binding to document the fact that we support eight wire buses" * tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: Document Octal mode as valid SPI bus width spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent calls spi: spi-fsl-dspi: Fix 16-bit word order in 32-bit XSPI mode spi: Don't look at TX buffer for PTP system timestamping spi: uniphier: Fix FIFO threshold
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commit
ec7b3f5372
@ -111,7 +111,7 @@ patternProperties:
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spi-rx-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 1, 2, 4 ]
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- enum: [ 1, 2, 4, 8 ]
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- default: 1
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description:
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Bus width to the SPI bus used for MISO.
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@ -123,7 +123,7 @@ patternProperties:
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spi-tx-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 1, 2, 4 ]
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- enum: [ 1, 2, 4, 8 ]
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- default: 1
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description:
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Bus width to the SPI bus used for MOSI.
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@ -172,9 +172,11 @@ static inline u32 rx_max(struct dw_spi *dws)
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static void dw_writer(struct dw_spi *dws)
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{
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u32 max = tx_max(dws);
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u32 max;
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u16 txw = 0;
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spin_lock(&dws->buf_lock);
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max = tx_max(dws);
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while (max--) {
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/* Set the tx word if the transfer's original "tx" is not null */
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if (dws->tx_end - dws->len) {
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@ -186,13 +188,16 @@ static void dw_writer(struct dw_spi *dws)
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dw_write_io_reg(dws, DW_SPI_DR, txw);
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dws->tx += dws->n_bytes;
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}
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spin_unlock(&dws->buf_lock);
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}
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static void dw_reader(struct dw_spi *dws)
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{
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u32 max = rx_max(dws);
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u32 max;
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u16 rxw;
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spin_lock(&dws->buf_lock);
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max = rx_max(dws);
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while (max--) {
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rxw = dw_read_io_reg(dws, DW_SPI_DR);
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/* Care rx only if the transfer's original "rx" is not null */
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@ -204,6 +209,7 @@ static void dw_reader(struct dw_spi *dws)
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}
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dws->rx += dws->n_bytes;
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}
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spin_unlock(&dws->buf_lock);
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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@ -276,18 +282,20 @@ static int dw_spi_transfer_one(struct spi_controller *master,
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{
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struct dw_spi *dws = spi_controller_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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unsigned long flags;
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u8 imask = 0;
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u16 txlevel = 0;
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u32 cr0;
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int ret;
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dws->dma_mapped = 0;
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spin_lock_irqsave(&dws->buf_lock, flags);
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dws->tx = (void *)transfer->tx_buf;
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dws->tx_end = dws->tx + transfer->len;
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dws->rx = transfer->rx_buf;
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dws->rx_end = dws->rx + transfer->len;
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dws->len = transfer->len;
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spin_unlock_irqrestore(&dws->buf_lock, flags);
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spi_enable_chip(dws, 0);
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@ -471,6 +479,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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dws->type = SSI_MOTO_SPI;
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dws->dma_inited = 0;
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dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
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spin_lock_init(&dws->buf_lock);
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spi_controller_set_devdata(master, dws);
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@ -119,6 +119,7 @@ struct dw_spi {
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size_t len;
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void *tx;
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void *tx_end;
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spinlock_t buf_lock;
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void *rx;
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void *rx_end;
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int dma_mapped;
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@ -185,6 +185,7 @@ struct fsl_dspi {
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struct spi_transfer *cur_transfer;
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struct spi_message *cur_msg;
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struct chip_data *cur_chip;
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size_t progress;
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size_t len;
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const void *tx;
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void *rx;
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@ -586,21 +587,14 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi)
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dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
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if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
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/* Write two TX FIFO entries first, and then the corresponding
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* CMD FIFO entry.
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/* Write the CMD FIFO entry first, and then the two
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* corresponding TX FIFO entries.
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*/
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u32 data = dspi_pop_tx(dspi);
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if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
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/* LSB */
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tx_fifo_write(dspi, data & 0xFFFF);
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tx_fifo_write(dspi, data >> 16);
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} else {
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/* MSB */
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tx_fifo_write(dspi, data >> 16);
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tx_fifo_write(dspi, data & 0xFFFF);
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}
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cmd_fifo_write(dspi);
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tx_fifo_write(dspi, data & 0xFFFF);
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tx_fifo_write(dspi, data >> 16);
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} else {
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/* Write one entry to both TX FIFO and CMD FIFO
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* simultaneously.
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@ -658,7 +652,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi)
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u32 spi_tcr;
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spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
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dspi->tx - dspi->bytes_per_word, !dspi->irq);
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dspi->progress, !dspi->irq);
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/* Get transfer counter (in number of SPI transfers). It was
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* reset to 0 when transfer(s) were started.
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@ -667,6 +661,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi)
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spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
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/* Update total number of bytes that were transferred */
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msg->actual_length += spi_tcnt * dspi->bytes_per_word;
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dspi->progress += spi_tcnt;
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trans_mode = dspi->devtype_data->trans_mode;
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if (trans_mode == DSPI_EOQ_MODE)
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@ -679,7 +674,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi)
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return 0;
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spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
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dspi->tx, !dspi->irq);
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dspi->progress, !dspi->irq);
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if (trans_mode == DSPI_EOQ_MODE)
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dspi_eoq_write(dspi);
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@ -768,6 +763,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr,
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dspi->rx = transfer->rx_buf;
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dspi->rx_end = dspi->rx + transfer->len;
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dspi->len = transfer->len;
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dspi->progress = 0;
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/* Validated transfer specific frame size (defaults applied) */
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dspi->bits_per_word = transfer->bits_per_word;
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if (transfer->bits_per_word <= 8)
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@ -789,7 +785,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr,
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SPI_CTARE_DTCP(1));
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spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
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dspi->tx, !dspi->irq);
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dspi->progress, !dspi->irq);
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trans_mode = dspi->devtype_data->trans_mode;
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switch (trans_mode) {
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@ -290,25 +290,32 @@ static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
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}
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}
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static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
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static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
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unsigned int threshold)
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{
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unsigned int fifo_threshold, fill_bytes;
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u32 val;
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fifo_threshold = DIV_ROUND_UP(priv->rx_bytes,
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bytes_per_word(priv->bits_per_word));
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fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
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fill_bytes = fifo_threshold - (priv->rx_bytes - priv->tx_bytes);
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/* set fifo threshold */
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val = readl(priv->base + SSI_FC);
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val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
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val |= FIELD_PREP(SSI_FC_TXFTH_MASK, fifo_threshold);
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val |= FIELD_PREP(SSI_FC_RXFTH_MASK, fifo_threshold);
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val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
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val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
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writel(val, priv->base + SSI_FC);
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}
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while (fill_bytes--)
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static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
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{
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unsigned int fifo_threshold, fill_words;
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unsigned int bpw = bytes_per_word(priv->bits_per_word);
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fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
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fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
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uniphier_spi_set_fifo_threshold(priv, fifo_threshold);
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fill_words = fifo_threshold -
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DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);
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while (fill_words--)
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uniphier_spi_send(priv);
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}
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@ -1499,8 +1499,7 @@ static void spi_pump_messages(struct kthread_work *work)
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* advances its @tx buffer pointer monotonically.
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* @ctlr: Pointer to the spi_controller structure of the driver
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* @xfer: Pointer to the transfer being timestamped
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* @tx: Pointer to the current word within the xfer->tx_buf that the driver is
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* preparing to transmit right now.
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* @progress: How many words (not bytes) have been transferred so far
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* @irqs_off: If true, will disable IRQs and preemption for the duration of the
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* transfer, for less jitter in time measurement. Only compatible
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* with PIO drivers. If true, must follow up with
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@ -1510,21 +1509,19 @@ static void spi_pump_messages(struct kthread_work *work)
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*/
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void spi_take_timestamp_pre(struct spi_controller *ctlr,
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struct spi_transfer *xfer,
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const void *tx, bool irqs_off)
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size_t progress, bool irqs_off)
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{
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u8 bytes_per_word = DIV_ROUND_UP(xfer->bits_per_word, 8);
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if (!xfer->ptp_sts)
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return;
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if (xfer->timestamped_pre)
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return;
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if (tx < (xfer->tx_buf + xfer->ptp_sts_word_pre * bytes_per_word))
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if (progress < xfer->ptp_sts_word_pre)
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return;
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/* Capture the resolution of the timestamp */
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xfer->ptp_sts_word_pre = (tx - xfer->tx_buf) / bytes_per_word;
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xfer->ptp_sts_word_pre = progress;
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xfer->timestamped_pre = true;
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@ -1546,23 +1543,20 @@ EXPORT_SYMBOL_GPL(spi_take_timestamp_pre);
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* timestamped.
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* @ctlr: Pointer to the spi_controller structure of the driver
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* @xfer: Pointer to the transfer being timestamped
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* @tx: Pointer to the current word within the xfer->tx_buf that the driver has
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* just transmitted.
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* @progress: How many words (not bytes) have been transferred so far
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* @irqs_off: If true, will re-enable IRQs and preemption for the local CPU.
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*/
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void spi_take_timestamp_post(struct spi_controller *ctlr,
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struct spi_transfer *xfer,
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const void *tx, bool irqs_off)
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size_t progress, bool irqs_off)
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{
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u8 bytes_per_word = DIV_ROUND_UP(xfer->bits_per_word, 8);
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if (!xfer->ptp_sts)
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return;
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if (xfer->timestamped_post)
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return;
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if (tx < (xfer->tx_buf + xfer->ptp_sts_word_post * bytes_per_word))
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if (progress < xfer->ptp_sts_word_post)
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return;
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ptp_read_system_postts(xfer->ptp_sts);
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@ -1573,7 +1567,7 @@ void spi_take_timestamp_post(struct spi_controller *ctlr,
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}
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/* Capture the resolution of the timestamp */
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xfer->ptp_sts_word_post = (tx - xfer->tx_buf) / bytes_per_word;
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xfer->ptp_sts_word_post = progress;
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xfer->timestamped_post = true;
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}
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@ -689,10 +689,10 @@ extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
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/* Helper calls for driver to timestamp transfer */
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void spi_take_timestamp_pre(struct spi_controller *ctlr,
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struct spi_transfer *xfer,
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const void *tx, bool irqs_off);
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size_t progress, bool irqs_off);
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void spi_take_timestamp_post(struct spi_controller *ctlr,
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struct spi_transfer *xfer,
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const void *tx, bool irqs_off);
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size_t progress, bool irqs_off);
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/* the spi driver core manages memory for the spi_controller classdev */
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extern struct spi_controller *__spi_alloc_controller(struct device *host,
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