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https://github.com/edk2-porting/linux-next.git
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forcedeth: fix multi irq issues
This patch fixes the issues with multiple irqs. I am resending based on feedback. I decoupled the dma mask for consistent memory and fixed leak with multiple irq in error path. Thanks to Manfred for catching the spin lock problem. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
3e0d167a6b
commit
ebf34c9b6f
@ -106,6 +106,7 @@
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* 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
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* 0.52: 20 Jan 2006: Add MSI/MSIX support.
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* 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
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* 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -117,7 +118,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.53"
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#define FORCEDETH_VERSION "0.54"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -710,6 +711,72 @@ static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
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}
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}
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static int using_multi_irqs(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
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return 0;
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else
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return 1;
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}
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static void nv_enable_irq(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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if (!using_multi_irqs(dev)) {
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if (np->msi_flags & NV_MSI_X_ENABLED)
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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enable_irq(dev->irq);
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} else {
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
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}
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}
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static void nv_disable_irq(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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if (!using_multi_irqs(dev)) {
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if (np->msi_flags & NV_MSI_X_ENABLED)
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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disable_irq(dev->irq);
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} else {
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
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}
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}
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/* In MSIX mode, a write to irqmask behaves as XOR */
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static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
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{
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u8 __iomem *base = get_hwbase(dev);
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writel(mask, base + NvRegIrqMask);
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}
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static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
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{
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struct fe_priv *np = get_nvpriv(dev);
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u8 __iomem *base = get_hwbase(dev);
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if (np->msi_flags & NV_MSI_X_ENABLED) {
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writel(mask, base + NvRegIrqMask);
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} else {
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if (np->msi_flags & NV_MSI_ENABLED)
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writel(0, base + NvRegMSIIrqMask);
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writel(0, base + NvRegIrqMask);
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}
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}
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#define MII_READ (-1)
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/* mii_rw: read/write a register on the PHY.
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*
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@ -1019,24 +1086,25 @@ static void nv_do_rx_refill(unsigned long data)
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struct net_device *dev = (struct net_device *) data;
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struct fe_priv *np = netdev_priv(dev);
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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disable_irq(dev->irq);
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if (!using_multi_irqs(dev)) {
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if (np->msi_flags & NV_MSI_X_ENABLED)
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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disable_irq(dev->irq);
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} else {
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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}
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if (nv_alloc_rx(dev)) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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if (!np->in_shutdown)
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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}
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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enable_irq(dev->irq);
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if (!using_multi_irqs(dev)) {
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if (np->msi_flags & NV_MSI_X_ENABLED)
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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enable_irq(dev->irq);
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} else {
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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}
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@ -1668,15 +1736,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
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* guessed, there is probably a simpler approach.
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* Changing the MTU is a rare event, it shouldn't matter.
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*/
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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disable_irq(dev->irq);
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} else {
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
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}
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nv_disable_irq(dev);
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spin_lock_bh(&dev->xmit_lock);
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spin_lock(&np->lock);
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/* stop engines */
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@ -1709,15 +1769,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
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nv_start_tx(dev);
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spin_unlock(&np->lock);
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spin_unlock_bh(&dev->xmit_lock);
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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enable_irq(dev->irq);
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} else {
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
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}
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nv_enable_irq(dev);
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}
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return 0;
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}
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@ -2108,16 +2160,16 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
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if (!(events & np->irqmask))
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break;
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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nv_tx_done(dev);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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if (events & (NVREG_IRQ_TX_ERR)) {
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dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
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dev->name, events);
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}
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if (i > max_interrupt_work) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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/* disable interrupts on the nic */
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writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
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pci_push(base);
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@ -2127,7 +2179,7 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
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mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
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}
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printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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break;
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}
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@ -2157,14 +2209,14 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
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nv_rx_process(dev);
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if (nv_alloc_rx(dev)) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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if (!np->in_shutdown)
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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}
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if (i > max_interrupt_work) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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/* disable interrupts on the nic */
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writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
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pci_push(base);
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@ -2174,7 +2226,7 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
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mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
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}
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printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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break;
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}
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@ -2203,14 +2255,14 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
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break;
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if (events & NVREG_IRQ_LINK) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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nv_link_irq(dev);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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}
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if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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nv_linkchange(dev);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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np->link_timeout = jiffies + LINK_TIMEOUT;
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}
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if (events & (NVREG_IRQ_UNKNOWN)) {
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@ -2218,7 +2270,7 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
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dev->name, events);
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}
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if (i > max_interrupt_work) {
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spin_lock(&np->lock);
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spin_lock_irq(&np->lock);
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/* disable interrupts on the nic */
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writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
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pci_push(base);
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@ -2228,7 +2280,7 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
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mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
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}
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printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
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spin_unlock(&np->lock);
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spin_unlock_irq(&np->lock);
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break;
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}
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@ -2251,10 +2303,11 @@ static void nv_do_nic_poll(unsigned long data)
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* nv_nic_irq because that may decide to do otherwise
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*/
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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disable_irq(dev->irq);
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if (!using_multi_irqs(dev)) {
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if (np->msi_flags & NV_MSI_X_ENABLED)
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disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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disable_irq(dev->irq);
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mask = np->irqmask;
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} else {
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if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
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@ -2277,11 +2330,12 @@ static void nv_do_nic_poll(unsigned long data)
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writel(mask, base + NvRegIrqMask);
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pci_push(base);
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if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
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((np->msi_flags & NV_MSI_X_ENABLED) &&
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((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) {
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if (!using_multi_irqs(dev)) {
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nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
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enable_irq(dev->irq);
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if (np->msi_flags & NV_MSI_X_ENABLED)
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enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
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else
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enable_irq(dev->irq);
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} else {
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if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
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nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL);
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@ -2628,6 +2682,113 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
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writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
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}
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static int nv_request_irq(struct net_device *dev)
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{
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struct fe_priv *np = get_nvpriv(dev);
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u8 __iomem *base = get_hwbase(dev);
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int ret = 1;
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int i;
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if (np->msi_flags & NV_MSI_X_CAPABLE) {
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for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
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np->msi_x_entry[i].entry = i;
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}
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if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
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np->msi_flags |= NV_MSI_X_ENABLED;
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if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
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/* Request irq for rx handling */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
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pci_disable_msix(np->pci_dev);
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np->msi_flags &= ~NV_MSI_X_ENABLED;
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goto out_err;
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}
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/* Request irq for tx handling */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
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pci_disable_msix(np->pci_dev);
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np->msi_flags &= ~NV_MSI_X_ENABLED;
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goto out_free_rx;
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}
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/* Request irq for link and timer handling */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
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pci_disable_msix(np->pci_dev);
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np->msi_flags &= ~NV_MSI_X_ENABLED;
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goto out_free_tx;
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}
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/* map interrupts to their respective vector */
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writel(0, base + NvRegMSIXMap0);
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writel(0, base + NvRegMSIXMap1);
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set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
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set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
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set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
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} else {
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/* Request irq for all interrupts */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
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pci_disable_msix(np->pci_dev);
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np->msi_flags &= ~NV_MSI_X_ENABLED;
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goto out_err;
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}
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/* map interrupts to vector 0 */
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writel(0, base + NvRegMSIXMap0);
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writel(0, base + NvRegMSIXMap1);
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}
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}
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}
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if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
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if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
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np->msi_flags |= NV_MSI_ENABLED;
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if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
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pci_disable_msi(np->pci_dev);
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np->msi_flags &= ~NV_MSI_ENABLED;
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goto out_err;
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}
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/* map interrupts to vector 0 */
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writel(0, base + NvRegMSIMap0);
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writel(0, base + NvRegMSIMap1);
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/* enable msi vector 0 */
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writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
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}
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}
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if (ret != 0) {
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if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0)
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goto out_err;
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}
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return 0;
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out_free_tx:
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free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
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out_free_rx:
|
||||
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
|
||||
out_err:
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void nv_free_irq(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *np = get_nvpriv(dev);
|
||||
int i;
|
||||
|
||||
if (np->msi_flags & NV_MSI_X_ENABLED) {
|
||||
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
|
||||
free_irq(np->msi_x_entry[i].vector, dev);
|
||||
}
|
||||
pci_disable_msix(np->pci_dev);
|
||||
np->msi_flags &= ~NV_MSI_X_ENABLED;
|
||||
} else {
|
||||
free_irq(np->pci_dev->irq, dev);
|
||||
if (np->msi_flags & NV_MSI_ENABLED) {
|
||||
pci_disable_msi(np->pci_dev);
|
||||
np->msi_flags &= ~NV_MSI_ENABLED;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int nv_open(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *np = netdev_priv(dev);
|
||||
@ -2720,12 +2881,16 @@ static int nv_open(struct net_device *dev)
|
||||
udelay(10);
|
||||
writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
|
||||
|
||||
writel(0, base + NvRegIrqMask);
|
||||
nv_disable_hw_interrupts(dev, np->irqmask);
|
||||
pci_push(base);
|
||||
writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
|
||||
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
|
||||
pci_push(base);
|
||||
|
||||
if (nv_request_irq(dev)) {
|
||||
goto out_drain;
|
||||
}
|
||||
|
||||
if (np->msi_flags & NV_MSI_X_CAPABLE) {
|
||||
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
|
||||
np->msi_x_entry[i].entry = i;
|
||||
@ -2799,7 +2964,7 @@ static int nv_open(struct net_device *dev)
|
||||
}
|
||||
|
||||
/* ask for interrupts */
|
||||
writel(np->irqmask, base + NvRegIrqMask);
|
||||
nv_enable_hw_interrupts(dev, np->irqmask);
|
||||
|
||||
spin_lock_irq(&np->lock);
|
||||
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
|
||||
@ -2843,7 +3008,6 @@ static int nv_close(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *np = netdev_priv(dev);
|
||||
u8 __iomem *base;
|
||||
int i;
|
||||
|
||||
spin_lock_irq(&np->lock);
|
||||
np->in_shutdown = 1;
|
||||
@ -2861,31 +3025,13 @@ static int nv_close(struct net_device *dev)
|
||||
|
||||
/* disable interrupts on the nic or we will lock up */
|
||||
base = get_hwbase(dev);
|
||||
if (np->msi_flags & NV_MSI_X_ENABLED) {
|
||||
writel(np->irqmask, base + NvRegIrqMask);
|
||||
} else {
|
||||
if (np->msi_flags & NV_MSI_ENABLED)
|
||||
writel(0, base + NvRegMSIIrqMask);
|
||||
writel(0, base + NvRegIrqMask);
|
||||
}
|
||||
nv_disable_hw_interrupts(dev, np->irqmask);
|
||||
pci_push(base);
|
||||
dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
|
||||
|
||||
spin_unlock_irq(&np->lock);
|
||||
|
||||
if (np->msi_flags & NV_MSI_X_ENABLED) {
|
||||
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
|
||||
free_irq(np->msi_x_entry[i].vector, dev);
|
||||
}
|
||||
pci_disable_msix(np->pci_dev);
|
||||
np->msi_flags &= ~NV_MSI_X_ENABLED;
|
||||
} else {
|
||||
free_irq(np->pci_dev->irq, dev);
|
||||
if (np->msi_flags & NV_MSI_ENABLED) {
|
||||
pci_disable_msi(np->pci_dev);
|
||||
np->msi_flags &= ~NV_MSI_ENABLED;
|
||||
}
|
||||
}
|
||||
nv_free_irq(dev);
|
||||
|
||||
drain_ring(dev);
|
||||
|
||||
@ -2974,20 +3120,18 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
|
||||
if (id->driver_data & DEV_HAS_HIGH_DMA) {
|
||||
/* packet format 3: supports 40-bit addressing */
|
||||
np->desc_ver = DESC_VER_3;
|
||||
np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
|
||||
if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
|
||||
printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
|
||||
pci_name(pci_dev));
|
||||
} else {
|
||||
if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
|
||||
printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
|
||||
pci_name(pci_dev));
|
||||
goto out_relreg;
|
||||
} else {
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
printk(KERN_INFO "forcedeth: using HIGHDMA\n");
|
||||
}
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
printk(KERN_INFO "forcedeth: using HIGHDMA\n");
|
||||
}
|
||||
if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
|
||||
printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
|
||||
pci_name(pci_dev));
|
||||
}
|
||||
np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
|
||||
} else if (id->driver_data & DEV_HAS_LARGEDESC) {
|
||||
/* packet format 2: supports jumbo frames */
|
||||
np->desc_ver = DESC_VER_2;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user