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thermal: small style cleanup in mtk_thermal
Remove all checkpatch.pl --strict errors, checks, and warnings. Cc: Zhang Rui <rui.zhang@intel.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-pm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Eduardo Valentin
parent
a92db1c808
commit
eb4fc33eb2
@ -78,7 +78,7 @@
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#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
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#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16
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#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
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#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
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#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
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@ -108,15 +108,15 @@
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#define MT8173_NUM_SENSORS_PER_ZONE 4
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/* Layout of the fuses providing the calibration data */
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#define MT8173_CALIB_BUF0_VALID (1 << 0)
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#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff)
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#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff)
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#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff)
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#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff)
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#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff)
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#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff)
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#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f)
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#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f)
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#define MT8173_CALIB_BUF0_VALID BIT(0)
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#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
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#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
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#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
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#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
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#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
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#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
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#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
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#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
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#define THERMAL_NAME "mtk-thermal"
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@ -136,6 +136,7 @@ struct mtk_thermal {
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struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
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/* lock: for getting and putting banks */
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struct mutex lock;
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/* Calibration values */
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@ -271,11 +272,9 @@ static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
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static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
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{
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struct mtk_thermal *mt = bank->mt;
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int temp, i, max;
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int i, temp = INT_MIN, max = INT_MIN;
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u32 raw;
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temp = max = INT_MIN;
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for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
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raw = readl(mt->thermal_base + sensing_points[i].msr);
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@ -322,7 +321,7 @@ static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
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};
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static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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u32 apmixed_phys_base, u32 auxadc_phys_base)
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u32 apmixed_phys_base, u32 auxadc_phys_base)
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{
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struct mtk_thermal_bank *bank = &mt->banks[num];
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const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
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@ -346,7 +345,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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/* poll is set to 10u */
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writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
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mt->thermal_base + TEMP_AHBPOLL);
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mt->thermal_base + TEMP_AHBPOLL);
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/* temperature sampling control, 1 sample */
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writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
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@ -375,49 +374,50 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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/* AHB address for auxadc mux selection */
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writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
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mt->thermal_base + TEMP_ADCMUXADDR);
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mt->thermal_base + TEMP_ADCMUXADDR);
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/* AHB address for pnp sensor mux selection */
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writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
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mt->thermal_base + TEMP_PNPMUXADDR);
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mt->thermal_base + TEMP_PNPMUXADDR);
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/* AHB value for auxadc enable */
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writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
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/* AHB address for auxadc enable (channel 0 immediate mode selected) */
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writel(auxadc_phys_base + AUXADC_CON1_SET_V,
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mt->thermal_base + TEMP_ADCENADDR);
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mt->thermal_base + TEMP_ADCENADDR);
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/* AHB address for auxadc valid bit */
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writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
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mt->thermal_base + TEMP_ADCVALIDADDR);
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mt->thermal_base + TEMP_ADCVALIDADDR);
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/* AHB address for auxadc voltage output */
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writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
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mt->thermal_base + TEMP_ADCVOLTADDR);
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mt->thermal_base + TEMP_ADCVOLTADDR);
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/* read valid & voltage are at the same register */
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writel(0x0, mt->thermal_base + TEMP_RDCTRL);
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/* indicate where the valid bit is */
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writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
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mt->thermal_base + TEMP_ADCVALIDMASK);
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mt->thermal_base + TEMP_ADCVALIDMASK);
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/* no shift */
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writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
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/* enable auxadc mux write transaction */
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writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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mt->thermal_base + TEMP_ADCWRITECTRL);
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for (i = 0; i < cfg->num_sensors; i++)
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writel(sensor_mux_values[cfg->sensors[i]],
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mt->thermal_base + sensing_points[i].adcpnp);
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mt->thermal_base + sensing_points[i].adcpnp);
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writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
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writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
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TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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mtk_thermal_put_bank(bank);
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}
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@ -434,7 +434,8 @@ static u64 of_get_phys_base(struct device_node *np)
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return of_translate_address(np, regaddr_p);
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}
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static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt)
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static int mtk_thermal_get_calibration_data(struct device *dev,
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struct mtk_thermal *mt)
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{
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struct nvmem_cell *cell;
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u32 *buf;
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@ -567,7 +568,8 @@ static int mtk_thermal_probe(struct platform_device *pdev)
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}
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for (i = 0; i < MT8173_NUM_ZONES; i++)
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mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base);
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mtk_thermal_init_bank(mt, i, apmixed_phys_base,
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auxadc_phys_base);
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platform_set_drvdata(pdev, mt);
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