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https://github.com/edk2-porting/linux-next.git
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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Titan defconfig update. sh: Fix IPR-IRQ's for IRQ-chip change breakage. sh: Update r7780rp_defconfig. video: Fix include in hp680_bl. sh: Wire up new syscalls.
This commit is contained in:
Linus Torvalds
commit
eafa6cb18e
@ -15,12 +15,16 @@
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#include <asm/io.h>
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#include <asm/machvec.h>
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static struct ipr_data hs77501rvoip_ipr_map[] = {
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#if defined(CONFIG_HS7751RVOIP_CODEC)
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{ DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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#endif
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};
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static void __init hs7751rvoip_init_irq(void)
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{
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#if defined(CONFIG_HS7751RVOIP_CODEC)
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make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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#endif
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make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map));
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init_hs7751rvoip_IRQ();
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}
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@ -13,6 +13,51 @@
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#include <asm/io.h>
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#include <asm/irq.h>
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static struct ipr_data sh7710voipgw_ipr_map[] = {
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{ TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY },
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{ WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY },
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/* SCIF0 */
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{ SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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/* DMAC-1 */
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{ DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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/* DMAC-2 */
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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/* IPSEC */
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{ IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY },
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/* EDMAC */
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{ EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, EDMAC0_PRIORITY },
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{ EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, EDMAC1_PRIORITY },
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{ EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, EDMAC2_PRIORITY },
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/* SIOF0 */
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{ SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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/* SIOF1 */
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{ SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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/* SLIC IRQ's */
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{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
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{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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@ -37,65 +82,7 @@ static void __init sh7710voipgw_init_irq(void)
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*/
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ctrl_outw(0x2aa, INTC_ICR1);
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/* Now make IPR interrupts */
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make_ipr_irq(TIMER2_IRQ, TIMER2_IPR_ADDR,
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TIMER2_IPR_POS, TIMER2_PRIORITY);
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make_ipr_irq(WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY);
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/* SCIF0 */
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make_ipr_irq(SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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/* DMAC-1 */
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make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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/* DMAC-2 */
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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/* IPSEC */
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make_ipr_irq(IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY);
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/* EDMAC */
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make_ipr_irq(EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS,
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EDMAC0_PRIORITY);
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make_ipr_irq(EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS,
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EDMAC1_PRIORITY);
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make_ipr_irq(EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS,
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EDMAC2_PRIORITY);
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/* SIOF0 */
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make_ipr_irq(SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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/* SIOF1 */
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make_ipr_irq(SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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/* SLIC IRQ's */
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make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
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make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
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make_ipr_irq(sh7710voipgw_ipr_map, ARRAY_SIZE(sh7710voipgw_ipr_map));
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}
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/*
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@ -13,6 +13,17 @@
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#include <asm/io.h>
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#include <asm/se7300.h>
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static struct ipr_data se7300_ipr_map[] = {
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/* PC_IRQ[0-3] -> IRQ0 (32) */
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{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ },
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/* A_IRQ[0-3] -> IRQ1 (33) */
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{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ },
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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@ -23,14 +34,7 @@ init_7300se_IRQ(void)
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ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */
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ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */
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/* PC_IRQ[0-3] -> IRQ0 (32) */
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make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ);
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/* A_IRQ[0-3] -> IRQ1 (33) */
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make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ);
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(se7300_ipr_map, ARRAY_SIZE(se7300_ipr_map));
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ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
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}
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@ -87,13 +87,38 @@ shmse_irq_demux(int irq)
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return irq;
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}
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static struct ipr_data se73180_siof0_ipr_map[] = {
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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};
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static struct ipr_data se73180_vpu_ipr_map[] = {
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{ VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
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};
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static struct ipr_data se73180_other_ipr_map[] = {
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
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/* VIO interrupt */
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{ CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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void __init
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init_73180se_IRQ(void)
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{
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map));
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ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
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ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */
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@ -101,27 +126,11 @@ init_73180se_IRQ(void)
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ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */
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make_intreq_irq(10);
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make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8);
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make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map));
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ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
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make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
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make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
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IIC0_PRIORITY);
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make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
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IIC0_PRIORITY);
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make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
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make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map));
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/* VIO interrupt */
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make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
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ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
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}
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@ -102,6 +102,51 @@ shmse_irq_demux(int irq)
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static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade",
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NULL, NULL};
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static struct ipr_data se7343_irq5_ipr_map[] = {
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{ IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
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};
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static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
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};
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static struct ipr_data se7343_other_ipr_map[] = {
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{ DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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/* I2C block */
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{ IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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/* SIOF */
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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/* SIU */
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{ SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
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/* VIO interrupt */
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{ CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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/*MFI interrupt*/
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{ MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
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/* LCD controller */
|
||||
{ LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
@ -138,54 +183,17 @@ init_7343se_IRQ(void)
|
||||
/* Setup all external interrupts to be active low */
|
||||
ctrl_outw(0xaaaa, INTC_ICR1);
|
||||
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
||||
make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
|
||||
|
||||
setup_irq(IRQ5_IRQ, &irq5);
|
||||
/* Set port control to use IRQ5 */
|
||||
*(u16 *)0xA4050108 &= ~0xc;
|
||||
|
||||
make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
|
||||
make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8);
|
||||
make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
|
||||
|
||||
ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
|
||||
|
||||
make_ipr_irq(DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
|
||||
make_ipr_irq(DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
|
||||
make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
|
||||
|
||||
/* I2C block */
|
||||
make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
|
||||
IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
|
||||
IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
|
||||
|
||||
make_ipr_irq(IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
|
||||
IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
|
||||
IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
|
||||
|
||||
/* SIOF */
|
||||
make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
|
||||
|
||||
/* SIU */
|
||||
make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
|
||||
|
||||
/* VIO interrupt */
|
||||
make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
|
||||
/*MFI interrupt*/
|
||||
|
||||
make_ipr_irq(MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY);
|
||||
|
||||
/* LCD controller */
|
||||
make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
|
||||
ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
|
||||
}
|
||||
|
||||
@ -13,6 +13,48 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/se.h>
|
||||
|
||||
static struct ipr_data se770x_ipr_map[] = {
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
/* This is default value */
|
||||
{ 0xf-0x2, BCR_ILCRA, 2, 0x2 },
|
||||
{ 0xf-0xa, BCR_ILCRA, 1, 0xa },
|
||||
{ 0xf-0x5, BCR_ILCRB, 0, 0x5 },
|
||||
{ 0xf-0x8, BCR_ILCRC, 1, 0x8 },
|
||||
{ 0xf-0xc, BCR_ILCRC, 0, 0xc },
|
||||
{ 0xf-0xe, BCR_ILCRD, 3, 0xe },
|
||||
{ 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */
|
||||
{ 0xf-0xd, BCR_ILCRE, 2, 0xd },
|
||||
{ 0xf-0x9, BCR_ILCRE, 1, 0x9 },
|
||||
{ 0xf-0x1, BCR_ILCRE, 0, 0x1 },
|
||||
{ 0xf-0xf, BCR_ILCRF, 3, 0xf },
|
||||
{ 0xf-0xb, BCR_ILCRF, 1, 0xb },
|
||||
{ 0xf-0x7, BCR_ILCRG, 3, 0x7 },
|
||||
{ 0xf-0x6, BCR_ILCRG, 2, 0x6 },
|
||||
{ 0xf-0x4, BCR_ILCRG, 1, 0x4 },
|
||||
#else
|
||||
{ 14, BCR_ILCRA, 2, 0x0f-14 },
|
||||
{ 12, BCR_ILCRA, 1, 0x0f-12 },
|
||||
{ 8, BCR_ILCRB, 1, 0x0f- 8 },
|
||||
{ 6, BCR_ILCRC, 3, 0x0f- 6 },
|
||||
{ 5, BCR_ILCRC, 2, 0x0f- 5 },
|
||||
{ 4, BCR_ILCRC, 1, 0x0f- 4 },
|
||||
{ 3, BCR_ILCRC, 0, 0x0f- 3 },
|
||||
{ 1, BCR_ILCRD, 3, 0x0f- 1 },
|
||||
|
||||
{ 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
|
||||
|
||||
{ 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
|
||||
{ 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
|
||||
{ 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
|
||||
{ 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
{ 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
|
||||
{ 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
@ -38,42 +80,6 @@ void __init init_se_IRQ(void)
|
||||
ctrl_outw(0, BCR_ILCRE);
|
||||
ctrl_outw(0, BCR_ILCRF);
|
||||
ctrl_outw(0, BCR_ILCRG);
|
||||
/* This is default value */
|
||||
make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2);
|
||||
make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa);
|
||||
make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5);
|
||||
make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8);
|
||||
make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc);
|
||||
make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe);
|
||||
make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */
|
||||
make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd);
|
||||
make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9);
|
||||
make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1);
|
||||
make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf);
|
||||
make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb);
|
||||
make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7);
|
||||
make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6);
|
||||
make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4);
|
||||
#else
|
||||
make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
|
||||
make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
|
||||
make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
|
||||
make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6);
|
||||
make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5);
|
||||
make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4);
|
||||
make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3);
|
||||
make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1);
|
||||
|
||||
make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */
|
||||
|
||||
make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */
|
||||
make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */
|
||||
make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */
|
||||
make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
|
||||
make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
|
||||
#endif
|
||||
make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
|
||||
}
|
||||
|
||||
@ -14,53 +14,50 @@
|
||||
#include <asm/irq.h>
|
||||
#include <asm/se7751.h>
|
||||
|
||||
static struct ipr_data se7751_ipr_map[] = {
|
||||
/* Leave old Solution Engine code in for reference. */
|
||||
#if defined(CONFIG_SH_SOLUTION_ENGINE)
|
||||
/*
|
||||
* Super I/O (Just mimic PC):
|
||||
* 1: keyboard
|
||||
* 3: serial 0
|
||||
* 4: serial 1
|
||||
* 5: printer
|
||||
* 6: floppy
|
||||
* 8: rtc
|
||||
* 12: mouse
|
||||
* 14: ide0
|
||||
*/
|
||||
{ 14, BCR_ILCRA, 2, 0x0f-14 },
|
||||
{ 12, BCR_ILCRA, 1, 0x0f-12 },
|
||||
{ 8, BCR_ILCRB, 1, 0x0f- 8 },
|
||||
{ 6, BCR_ILCRC, 3, 0x0f- 6 },
|
||||
{ 5, BCR_ILCRC, 2, 0x0f- 5 },
|
||||
{ 4, BCR_ILCRC, 1, 0x0f- 4 },
|
||||
{ 3, BCR_ILCRC, 0, 0x0f- 3 },
|
||||
{ 1, BCR_ILCRD, 3, 0x0f- 1 },
|
||||
|
||||
{ 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
|
||||
|
||||
{ 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
|
||||
{ 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
|
||||
{ 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
|
||||
{ 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
{ 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
|
||||
{ 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
|
||||
#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
|
||||
{ 13, BCR_ILCRD, 3, 2 },
|
||||
/* Add additional entries here as drivers are added and tested. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
void __init init_7751se_IRQ(void)
|
||||
{
|
||||
|
||||
/* Leave old Solution Engine code in for reference. */
|
||||
#if defined(CONFIG_SH_SOLUTION_ENGINE)
|
||||
/*
|
||||
* Super I/O (Just mimic PC):
|
||||
* 1: keyboard
|
||||
* 3: serial 0
|
||||
* 4: serial 1
|
||||
* 5: printer
|
||||
* 6: floppy
|
||||
* 8: rtc
|
||||
* 12: mouse
|
||||
* 14: ide0
|
||||
*/
|
||||
make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
|
||||
make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
|
||||
make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
|
||||
make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6);
|
||||
make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5);
|
||||
make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4);
|
||||
make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3);
|
||||
make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1);
|
||||
|
||||
make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */
|
||||
|
||||
make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */
|
||||
make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */
|
||||
make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */
|
||||
make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
|
||||
make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
|
||||
|
||||
#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
|
||||
|
||||
make_ipr_irq(13, BCR_ILCRD, 3, 2);
|
||||
|
||||
/* Add additional calls to make_ipr_irq() as drivers are added
|
||||
* and tested.
|
||||
*/
|
||||
#endif
|
||||
|
||||
make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map));
|
||||
}
|
||||
|
||||
@ -14,14 +14,17 @@
|
||||
#include <asm/sh03/sh03.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
static struct ipr_data sh03_ipr_map[] = {
|
||||
{ IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
|
||||
{ IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
|
||||
{ IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
|
||||
{ IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
|
||||
};
|
||||
|
||||
static void __init init_sh03_IRQ(void)
|
||||
{
|
||||
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
|
||||
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
make_ipr_irq(sh03_ipr_map, ARRAY_SIZE(sh03_ipr_map));
|
||||
}
|
||||
|
||||
extern void *cf_io_base;
|
||||
|
||||
@ -68,6 +68,13 @@ module_init(eraseconfig_init);
|
||||
* IRL3 = crypto
|
||||
*/
|
||||
|
||||
static struct ipr_data snapgear_ipr_map[] = {
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
};
|
||||
|
||||
static void __init init_snapgear_IRQ(void)
|
||||
{
|
||||
/* enable individual interrupt mode for externals */
|
||||
@ -75,10 +82,7 @@ static void __init init_snapgear_IRQ(void)
|
||||
|
||||
printk("Setup SnapGear IRQ/IPR ...\n");
|
||||
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
make_ipr_irq(snapgear_ipr_map, ARRAY_SIZE(snapgear_ipr_map));
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -9,15 +9,19 @@
|
||||
|
||||
extern void __init pcibios_init_platform(void);
|
||||
|
||||
static struct ipr_data titan_ipr_map[] = {
|
||||
{ TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
|
||||
{ TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
|
||||
{ TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
|
||||
{ TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
|
||||
};
|
||||
|
||||
static void __init init_titan_irq(void)
|
||||
{
|
||||
/* enable individual interrupt mode for externals */
|
||||
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
|
||||
|
||||
make_ipr_irq( TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); /* PCIRQ0 */
|
||||
make_ipr_irq( TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); /* PCIRQ1 */
|
||||
make_ipr_irq( TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); /* PCIRQ2 */
|
||||
make_ipr_irq( TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); /* PCIRQ3 */
|
||||
make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map));
|
||||
}
|
||||
|
||||
struct sh_machine_vector mv_titan __initmv = {
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.18
|
||||
# Tue Oct 3 11:32:47 2006
|
||||
# Linux kernel version: 2.6.19-rc3
|
||||
# Tue Oct 31 12:32:06 2006
|
||||
#
|
||||
CONFIG_SUPERH=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
@ -10,6 +10,7 @@ CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
# CONFIG_GENERIC_TIME is not set
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
@ -178,7 +179,7 @@ CONFIG_MMU=y
|
||||
CONFIG_PAGE_OFFSET=0x80000000
|
||||
CONFIG_MEMORY_START=0x08000000
|
||||
CONFIG_MEMORY_SIZE=0x08000000
|
||||
CONFIG_32BIT=y
|
||||
# CONFIG_32BIT is not set
|
||||
CONFIG_VSYSCALL=y
|
||||
CONFIG_HUGETLB_PAGE_SIZE_64K=y
|
||||
# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
|
||||
@ -229,9 +230,7 @@ CONFIG_SH_PCLK_FREQ=32000000
|
||||
#
|
||||
# DMA support
|
||||
#
|
||||
CONFIG_SH_DMA=y
|
||||
CONFIG_NR_ONCHIP_DMA_CHANNELS=6
|
||||
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
|
||||
# CONFIG_SH_DMA is not set
|
||||
|
||||
#
|
||||
# Companion Chips
|
||||
@ -259,7 +258,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000
|
||||
CONFIG_BOOT_LINK_OFFSET=0x00800000
|
||||
# CONFIG_UBC_WAKEUP is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/hda1"
|
||||
CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/sda1"
|
||||
|
||||
#
|
||||
# Bus options
|
||||
@ -336,6 +335,7 @@ CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
@ -440,77 +440,29 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
CONFIG_IDE=m
|
||||
CONFIG_IDE_MAX_HWIFS=4
|
||||
CONFIG_BLK_DEV_IDE=m
|
||||
|
||||
#
|
||||
# Please see Documentation/ide.txt for help/info on IDE drives
|
||||
#
|
||||
CONFIG_BLK_DEV_IDE_SATA=y
|
||||
CONFIG_BLK_DEV_IDEDISK=m
|
||||
CONFIG_IDEDISK_MULTI_MODE=y
|
||||
# CONFIG_BLK_DEV_IDECD is not set
|
||||
# CONFIG_BLK_DEV_IDETAPE is not set
|
||||
# CONFIG_BLK_DEV_IDEFLOPPY is not set
|
||||
CONFIG_BLK_DEV_IDESCSI=m
|
||||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
|
||||
#
|
||||
# IDE chipset support/bugfixes
|
||||
#
|
||||
CONFIG_IDE_GENERIC=m
|
||||
CONFIG_BLK_DEV_IDEPCI=y
|
||||
CONFIG_IDEPCI_SHARE_IRQ=y
|
||||
# CONFIG_BLK_DEV_OFFBOARD is not set
|
||||
CONFIG_BLK_DEV_GENERIC=m
|
||||
# CONFIG_BLK_DEV_OPTI621 is not set
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
|
||||
CONFIG_IDEDMA_PCI_AUTO=y
|
||||
# CONFIG_IDEDMA_ONLYDISK is not set
|
||||
CONFIG_BLK_DEV_AEC62XX=m
|
||||
# CONFIG_BLK_DEV_ALI15X3 is not set
|
||||
# CONFIG_BLK_DEV_AMD74XX is not set
|
||||
# CONFIG_BLK_DEV_CMD64X is not set
|
||||
# CONFIG_BLK_DEV_TRIFLEX is not set
|
||||
# CONFIG_BLK_DEV_CY82C693 is not set
|
||||
# CONFIG_BLK_DEV_CS5520 is not set
|
||||
# CONFIG_BLK_DEV_CS5530 is not set
|
||||
# CONFIG_BLK_DEV_HPT34X is not set
|
||||
# CONFIG_BLK_DEV_HPT366 is not set
|
||||
# CONFIG_BLK_DEV_SC1200 is not set
|
||||
# CONFIG_BLK_DEV_PIIX is not set
|
||||
# CONFIG_BLK_DEV_IT821X is not set
|
||||
# CONFIG_BLK_DEV_NS87415 is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
|
||||
CONFIG_BLK_DEV_PDC202XX_NEW=m
|
||||
# CONFIG_BLK_DEV_SVWKS is not set
|
||||
CONFIG_BLK_DEV_SIIMAGE=m
|
||||
# CONFIG_BLK_DEV_SLC90E66 is not set
|
||||
# CONFIG_BLK_DEV_TRM290 is not set
|
||||
# CONFIG_BLK_DEV_VIA82CXXX is not set
|
||||
# CONFIG_IDE_ARM is not set
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
# CONFIG_IDEDMA_IVB is not set
|
||||
CONFIG_IDEDMA_AUTO=y
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
CONFIG_SCSI=m
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
|
||||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
#
|
||||
CONFIG_BLK_DEV_SD=m
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_CHR_DEV_ST is not set
|
||||
# CONFIG_CHR_DEV_OSST is not set
|
||||
# CONFIG_BLK_DEV_SR is not set
|
||||
@ -561,6 +513,7 @@ CONFIG_CHR_DEV_SG=m
|
||||
# CONFIG_SCSI_IPR is not set
|
||||
# CONFIG_SCSI_QLOGIC_1280 is not set
|
||||
# CONFIG_SCSI_QLA_FC is not set
|
||||
# CONFIG_SCSI_QLA_ISCSI is not set
|
||||
# CONFIG_SCSI_LPFC is not set
|
||||
# CONFIG_SCSI_DC395x is not set
|
||||
# CONFIG_SCSI_DC390T is not set
|
||||
@ -570,7 +523,55 @@ CONFIG_CHR_DEV_SG=m
|
||||
#
|
||||
# Serial ATA (prod) and Parallel ATA (experimental) drivers
|
||||
#
|
||||
# CONFIG_ATA is not set
|
||||
CONFIG_ATA=y
|
||||
# CONFIG_SATA_AHCI is not set
|
||||
# CONFIG_SATA_SVW is not set
|
||||
# CONFIG_ATA_PIIX is not set
|
||||
# CONFIG_SATA_MV is not set
|
||||
# CONFIG_SATA_NV is not set
|
||||
# CONFIG_PDC_ADMA is not set
|
||||
# CONFIG_SATA_QSTOR is not set
|
||||
# CONFIG_SATA_PROMISE is not set
|
||||
# CONFIG_SATA_SX4 is not set
|
||||
CONFIG_SATA_SIL=y
|
||||
# CONFIG_SATA_SIL24 is not set
|
||||
# CONFIG_SATA_SIS is not set
|
||||
# CONFIG_SATA_ULI is not set
|
||||
# CONFIG_SATA_VIA is not set
|
||||
# CONFIG_SATA_VITESSE is not set
|
||||
# CONFIG_PATA_ALI is not set
|
||||
# CONFIG_PATA_AMD is not set
|
||||
# CONFIG_PATA_ARTOP is not set
|
||||
# CONFIG_PATA_ATIIXP is not set
|
||||
# CONFIG_PATA_CMD64X is not set
|
||||
# CONFIG_PATA_CS5520 is not set
|
||||
# CONFIG_PATA_CS5530 is not set
|
||||
# CONFIG_PATA_CYPRESS is not set
|
||||
# CONFIG_PATA_EFAR is not set
|
||||
# CONFIG_ATA_GENERIC is not set
|
||||
# CONFIG_PATA_HPT366 is not set
|
||||
# CONFIG_PATA_HPT37X is not set
|
||||
# CONFIG_PATA_HPT3X2N is not set
|
||||
# CONFIG_PATA_HPT3X3 is not set
|
||||
# CONFIG_PATA_IT821X is not set
|
||||
# CONFIG_PATA_JMICRON is not set
|
||||
# CONFIG_PATA_TRIFLEX is not set
|
||||
# CONFIG_PATA_MPIIX is not set
|
||||
# CONFIG_PATA_OLDPIIX is not set
|
||||
# CONFIG_PATA_NETCELL is not set
|
||||
# CONFIG_PATA_NS87410 is not set
|
||||
# CONFIG_PATA_OPTI is not set
|
||||
# CONFIG_PATA_OPTIDMA is not set
|
||||
# CONFIG_PATA_PDC_OLD is not set
|
||||
# CONFIG_PATA_RADISYS is not set
|
||||
# CONFIG_PATA_RZ1000 is not set
|
||||
# CONFIG_PATA_SC1200 is not set
|
||||
# CONFIG_PATA_SERVERWORKS is not set
|
||||
# CONFIG_PATA_PDC2027X is not set
|
||||
# CONFIG_PATA_SIL680 is not set
|
||||
# CONFIG_PATA_SIS is not set
|
||||
# CONFIG_PATA_VIA is not set
|
||||
# CONFIG_PATA_WINBOND is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
@ -840,7 +841,6 @@ CONFIG_HW_RANDOM=y
|
||||
# TPM devices
|
||||
#
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_TELCLOCK is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
@ -856,6 +856,7 @@ CONFIG_HW_RANDOM=y
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
@ -867,15 +868,10 @@ CONFIG_HWMON=y
|
||||
# CONFIG_SENSORS_VT1211 is not set
|
||||
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
@ -959,7 +955,29 @@ CONFIG_USB_ARCH_HAS_EHCI=y
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_HCTOSYS=y
|
||||
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||
# CONFIG_RTC_DEBUG is not set
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
|
||||
#
|
||||
# RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
# CONFIG_RTC_DRV_DS1742 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
CONFIG_RTC_DRV_SH=y
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
@ -984,6 +1002,7 @@ CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
@ -991,6 +1010,7 @@ CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_JFS_FS is not set
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
CONFIG_MINIX_FS=y
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
@ -1027,7 +1047,8 @@ CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
# CONFIG_TMPFS is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_RAMFS=y
|
||||
@ -1159,6 +1180,7 @@ CONFIG_DEBUG_FS=y
|
||||
# CONFIG_DEBUG_LIST is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FORCED_INLINING=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_SH_STANDARD_BIOS is not set
|
||||
# CONFIG_EARLY_SCIF_CONSOLE is not set
|
||||
@ -1178,9 +1200,9 @@ CONFIG_FORCED_INLINING=y
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=m
|
||||
CONFIG_CRYPTO_BLKCIPHER=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=m
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
@ -1191,7 +1213,7 @@ CONFIG_CRYPTO_MD5=y
|
||||
# CONFIG_CRYPTO_WP512 is not set
|
||||
# CONFIG_CRYPTO_TGR192 is not set
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_CBC=m
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_BLOWFISH is not set
|
||||
# CONFIG_CRYPTO_TWOFISH is not set
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.18
|
||||
# Tue Oct 3 12:59:14 2006
|
||||
# Linux kernel version: 2.6.19-rc3
|
||||
# Mon Oct 30 18:04:49 2006
|
||||
#
|
||||
CONFIG_SUPERH=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
@ -10,6 +10,7 @@ CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
# CONFIG_GENERIC_TIME is not set
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
@ -23,7 +24,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_IPC_NS is not set
|
||||
@ -236,8 +237,8 @@ CONFIG_HZ_250=y
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_KEXEC is not set
|
||||
# CONFIG_SMP is not set
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
# CONFIG_PREEMPT is not set
|
||||
|
||||
#
|
||||
@ -247,7 +248,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000
|
||||
CONFIG_BOOT_LINK_OFFSET=0x009e0000
|
||||
# CONFIG_UBC_WAKEUP is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttySC1,38400N81 root=/dev/nfs ip=:::::eth1:autoconf"
|
||||
CONFIG_CMDLINE="console=ttySC1,38400N81 root=/dev/nfs ip=:::::eth1:autoconf rw"
|
||||
|
||||
#
|
||||
# Bus options
|
||||
@ -334,6 +335,7 @@ CONFIG_INET_XFRM_TUNNEL=y
|
||||
CONFIG_INET_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=m
|
||||
CONFIG_INET_TCP_DIAG=m
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
@ -355,9 +357,10 @@ CONFIG_INET6_XFRM_TUNNEL=y
|
||||
CONFIG_INET6_TUNNEL=y
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET6_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
|
||||
CONFIG_IPV6_SIT=m
|
||||
CONFIG_IPV6_TUNNEL=y
|
||||
# CONFIG_IPV6_SUBTREES is not set
|
||||
# CONFIG_IPV6_MULTIPLE_TABLES is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
CONFIG_NETFILTER=y
|
||||
@ -713,6 +716,12 @@ CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
CONFIG_ATA_OVER_ETH=m
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
@ -778,9 +787,9 @@ CONFIG_CHR_DEV_SG=m
|
||||
# CONFIG_SCSI_INIA100 is not set
|
||||
# CONFIG_SCSI_STEX is not set
|
||||
# CONFIG_SCSI_SYM53C8XX_2 is not set
|
||||
# CONFIG_SCSI_IPR is not set
|
||||
# CONFIG_SCSI_QLOGIC_1280 is not set
|
||||
# CONFIG_SCSI_QLA_FC is not set
|
||||
# CONFIG_SCSI_QLA_ISCSI is not set
|
||||
# CONFIG_SCSI_LPFC is not set
|
||||
# CONFIG_SCSI_DC395x is not set
|
||||
# CONFIG_SCSI_DC390T is not set
|
||||
@ -1095,7 +1104,6 @@ CONFIG_HW_RANDOM=y
|
||||
# TPM devices
|
||||
#
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_TELCLOCK is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
@ -1123,15 +1131,10 @@ CONFIG_HWMON=y
|
||||
# CONFIG_SENSORS_VT1211 is not set
|
||||
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
@ -1177,9 +1180,9 @@ CONFIG_USB_DEVICEFS=y
|
||||
# USB Host Controller Drivers
|
||||
#
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_SPLIT_ISO is not set
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_SPLIT_ISO=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_EHCI_TT_NEWSCHED=y
|
||||
# CONFIG_USB_ISP116X_HCD is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
# CONFIG_USB_OHCI_BIG_ENDIAN is not set
|
||||
@ -1235,7 +1238,6 @@ CONFIG_USB_STORAGE=y
|
||||
# CONFIG_USB_ATI_REMOTE2 is not set
|
||||
# CONFIG_USB_KEYSPAN_REMOTE is not set
|
||||
# CONFIG_USB_APPLETOUCH is not set
|
||||
# CONFIG_USB_TRANCEVIBRATOR is not set
|
||||
|
||||
#
|
||||
# USB Imaging devices
|
||||
@ -1246,11 +1248,20 @@ CONFIG_USB_STORAGE=y
|
||||
#
|
||||
# USB Network Adapters
|
||||
#
|
||||
# CONFIG_USB_CATC is not set
|
||||
# CONFIG_USB_KAWETH is not set
|
||||
# CONFIG_USB_PEGASUS is not set
|
||||
# CONFIG_USB_RTL8150 is not set
|
||||
# CONFIG_USB_USBNET is not set
|
||||
CONFIG_USB_CATC=m
|
||||
CONFIG_USB_KAWETH=m
|
||||
CONFIG_USB_PEGASUS=m
|
||||
CONFIG_USB_RTL8150=m
|
||||
CONFIG_USB_USBNET=m
|
||||
CONFIG_USB_NET_AX8817X=m
|
||||
CONFIG_USB_NET_CDCETHER=m
|
||||
# CONFIG_USB_NET_GL620A is not set
|
||||
CONFIG_USB_NET_NET1080=m
|
||||
CONFIG_USB_NET_PLUSB=m
|
||||
# CONFIG_USB_NET_MCS7830 is not set
|
||||
# CONFIG_USB_NET_RNDIS_HOST is not set
|
||||
# CONFIG_USB_NET_CDC_SUBSET is not set
|
||||
CONFIG_USB_NET_ZAURUS=m
|
||||
CONFIG_USB_MON=y
|
||||
|
||||
#
|
||||
@ -1285,6 +1296,7 @@ CONFIG_USB_SERIAL_ARK3116=m
|
||||
# CONFIG_USB_SERIAL_KLSI is not set
|
||||
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
|
||||
# CONFIG_USB_SERIAL_MCT_U232 is not set
|
||||
# CONFIG_USB_SERIAL_MOS7720 is not set
|
||||
# CONFIG_USB_SERIAL_MOS7840 is not set
|
||||
# CONFIG_USB_SERIAL_NAVMAN is not set
|
||||
CONFIG_USB_SERIAL_PL2303=m
|
||||
@ -1316,6 +1328,7 @@ CONFIG_USB_SERIAL_PL2303=m
|
||||
# CONFIG_USB_APPLEDISPLAY is not set
|
||||
# CONFIG_USB_SISUSBVGA is not set
|
||||
# CONFIG_USB_LD is not set
|
||||
# CONFIG_USB_TRANCEVIBRATOR is not set
|
||||
# CONFIG_USB_TEST is not set
|
||||
|
||||
#
|
||||
@ -1357,7 +1370,26 @@ CONFIG_USB_SERIAL_PL2303=m
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
CONFIG_RTC_LIB=m
|
||||
CONFIG_RTC_CLASS=m
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=m
|
||||
CONFIG_RTC_INTF_PROC=m
|
||||
CONFIG_RTC_INTF_DEV=m
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
|
||||
#
|
||||
# RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
# CONFIG_RTC_DRV_DS1742 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
CONFIG_RTC_DRV_SH=m
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
@ -1380,8 +1412,12 @@ CONFIG_EXT2_FS=y
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_FS_XATTR is not set
|
||||
CONFIG_EXT4DEV_FS=m
|
||||
# CONFIG_EXT4DEV_FS_XATTR is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_JBD2=m
|
||||
# CONFIG_JBD2_DEBUG is not set
|
||||
CONFIG_REISERFS_FS=m
|
||||
# CONFIG_REISERFS_CHECK is not set
|
||||
# CONFIG_REISERFS_PROC_INFO is not set
|
||||
@ -1393,9 +1429,10 @@ CONFIG_XFS_FS=m
|
||||
# CONFIG_XFS_SECURITY is not set
|
||||
# CONFIG_XFS_POSIX_ACL is not set
|
||||
# CONFIG_XFS_RT is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_ROMFS_FS=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
@ -1480,7 +1517,12 @@ CONFIG_SUNRPC=y
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
CONFIG_SMB_FS=m
|
||||
# CONFIG_SMB_NLS_DEFAULT is not set
|
||||
# CONFIG_CIFS is not set
|
||||
CONFIG_CIFS=m
|
||||
# CONFIG_CIFS_STATS is not set
|
||||
CONFIG_CIFS_WEAK_PW_HASH=y
|
||||
# CONFIG_CIFS_XATTR is not set
|
||||
# CONFIG_CIFS_DEBUG2 is not set
|
||||
# CONFIG_CIFS_EXPERIMENTAL is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
@ -1583,9 +1625,10 @@ CONFIG_LOG_BUF_SHIFT=16
|
||||
# CONFIG_DEBUG_LIST is not set
|
||||
# CONFIG_FRAME_POINTER is not set
|
||||
# CONFIG_FORCED_INLINING is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_SH_STANDARD_BIOS is not set
|
||||
CONFIG_EARLY_SCIF_CONSOLE=y
|
||||
# CONFIG_EARLY_SCIF_CONSOLE is not set
|
||||
# CONFIG_EARLY_PRINTK is not set
|
||||
# CONFIG_DEBUG_STACKOVERFLOW is not set
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
@ -1605,7 +1648,7 @@ CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=m
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_MD4=m
|
||||
@ -1615,7 +1658,7 @@ CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
|
||||
@ -19,23 +19,34 @@
|
||||
#include <asm/io.h>
|
||||
#include "dma-sh.h"
|
||||
|
||||
static inline unsigned int get_dmte_irq(unsigned int chan)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
static struct ipr_data dmae_ipr_map[] = {
|
||||
{ DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
};
|
||||
#endif
|
||||
static struct ipr_data dmte_ipr_map[] = {
|
||||
/*
|
||||
* Normally we could just do DMTE0_IRQ + chan outright, though in the
|
||||
* case of the 7751R, the DMTE IRQs for channels > 4 start right above
|
||||
* the SCIF
|
||||
*/
|
||||
if (chan < 4) {
|
||||
irq = DMTE0_IRQ + chan;
|
||||
} else {
|
||||
#ifdef DMTE4_IRQ
|
||||
irq = DMTE4_IRQ + chan - 4;
|
||||
#endif
|
||||
}
|
||||
{ DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
};
|
||||
|
||||
static inline unsigned int get_dmte_irq(unsigned int chan)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
if (chan < ARRAY_SIZE(dmte_ipr_map))
|
||||
irq = dmte_ipr_map[chan].irq;
|
||||
return irq;
|
||||
}
|
||||
|
||||
@ -258,17 +269,16 @@ static int __init sh_dmac_init(void)
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
|
||||
make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
|
||||
i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
|
||||
if (unlikely(i < 0))
|
||||
return i;
|
||||
#endif
|
||||
|
||||
for (i = 0; i < info->nr_channels; i++) {
|
||||
int irq = get_dmte_irq(i);
|
||||
|
||||
make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
|
||||
}
|
||||
i = info->nr_channels;
|
||||
if (i > ARRAY_SIZE(dmte_ipr_map))
|
||||
i = ARRAY_SIZE(dmte_ipr_map);
|
||||
make_ipr_irq(dmte_ipr_map, i);
|
||||
|
||||
/*
|
||||
* Initialize DMAOR, and clean up any error flags that may have
|
||||
|
||||
@ -23,24 +23,21 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
struct ipr_data {
|
||||
unsigned int addr; /* Address of Interrupt Priority Register */
|
||||
int shift; /* Shifts of the 16-bit data */
|
||||
int priority; /* The priority */
|
||||
};
|
||||
|
||||
static void disable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
int shift = p->shift*4;
|
||||
/* Set the priority in IPR to 0 */
|
||||
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
|
||||
}
|
||||
|
||||
static void enable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
int shift = p->shift*4;
|
||||
/* Set priority in IPR back to original value */
|
||||
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
|
||||
}
|
||||
|
||||
static struct irq_chip ipr_irq_chip = {
|
||||
@ -50,67 +47,57 @@ static struct irq_chip ipr_irq_chip = {
|
||||
.mask_ack = disable_ipr_irq,
|
||||
};
|
||||
|
||||
void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
|
||||
void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
|
||||
{
|
||||
struct ipr_data ipr_data;
|
||||
int i;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
ipr_data.addr = addr;
|
||||
ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
|
||||
ipr_data.priority = priority;
|
||||
|
||||
set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
unsigned int irq = table[i].irq;
|
||||
disable_irq_nosync(irq);
|
||||
set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_chip_data(irq, &ipr_data);
|
||||
|
||||
enable_ipr_irq(irq);
|
||||
set_irq_chip_data(irq, &table[i]);
|
||||
enable_ipr_irq(irq);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(make_ipr_irq);
|
||||
|
||||
/* XXX: This needs to die a horrible death.. */
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static struct ipr_data sys_ipr_map[] = {
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
||||
make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
|
||||
make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
|
||||
{ TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
|
||||
{ TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
|
||||
#ifdef RTC_IRQ
|
||||
make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
|
||||
{ RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCI_ERI_IRQ
|
||||
make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
{ SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
{ SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
{ SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCIF1_ERI_IRQ
|
||||
make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
{ SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
{ SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
|
||||
{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
|
||||
{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
|
||||
{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCIF_ERI_IRQ
|
||||
make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
{ SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef IRDA_ERI_IRQ
|
||||
make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
{ IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
@ -124,14 +111,19 @@ void __init init_IRQ(void)
|
||||
* You should set corresponding bits of PFC to "00"
|
||||
* to enable these interrupts.
|
||||
*/
|
||||
make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
|
||||
make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
|
||||
make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
|
||||
make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
|
||||
make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
||||
{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
|
||||
{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
|
||||
{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
|
||||
{ IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
|
||||
{ IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
|
||||
{ IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PINT_IRQ
|
||||
init_IRQ_pint();
|
||||
@ -153,5 +145,3 @@ int ipr_irq_demux(int irq)
|
||||
return irq;
|
||||
}
|
||||
#endif
|
||||
|
||||
EXPORT_SYMBOL(make_ipr_irq);
|
||||
|
||||
@ -84,12 +84,16 @@ void make_pint_irq(unsigned int irq)
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
|
||||
static struct ipr_data pint_ipr_map[] = {
|
||||
{ PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY },
|
||||
{ PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY },
|
||||
};
|
||||
|
||||
void __init init_IRQ_pint(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
|
||||
make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
|
||||
make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map));
|
||||
|
||||
enable_irq(PINT0_IRQ);
|
||||
enable_irq(PINT8_IRQ);
|
||||
|
||||
@ -351,3 +351,6 @@ ENTRY(sys_call_table)
|
||||
.long sys_sync_file_range
|
||||
.long sys_tee /* 315 */
|
||||
.long sys_vmsplice
|
||||
.long sys_move_pages
|
||||
.long sys_getcpu
|
||||
.long sys_epoll_pwait
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include <linux/backlight.h>
|
||||
|
||||
#include <asm/cpu/dac.h>
|
||||
#include <asm/hp6xx/hp6xx.h>
|
||||
#include <asm/hp6xx.h>
|
||||
#include <asm/hd64461.h>
|
||||
|
||||
#define HP680_MAX_INTENSITY 255
|
||||
|
||||
@ -327,11 +327,17 @@ extern unsigned short *irq_mask_register;
|
||||
*/
|
||||
void init_IRQ_pint(void);
|
||||
|
||||
struct ipr_data {
|
||||
unsigned int irq;
|
||||
unsigned int addr; /* Address of Interrupt Priority Register */
|
||||
int shift; /* Shifts of the 16-bit data */
|
||||
int priority; /* The priority */
|
||||
};
|
||||
|
||||
/*
|
||||
* Function for "on chip support modules".
|
||||
*/
|
||||
extern void make_ipr_irq(unsigned int irq, unsigned int addr,
|
||||
int pos, int priority);
|
||||
extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
|
||||
extern void make_imask_irq(unsigned int irq);
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
|
||||
@ -324,8 +324,11 @@
|
||||
#define __NR_sync_file_range 314
|
||||
#define __NR_tee 315
|
||||
#define __NR_vmsplice 316
|
||||
#define __NR_move_pages 317
|
||||
#define __NR_getcpu 318
|
||||
#define __NR_epoll_pwait 319
|
||||
|
||||
#define NR_syscalls 317
|
||||
#define NR_syscalls 320
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user