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clk: ingenic: jz4725b: Add UDC PHY clock

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Add clock for the USB Device Controller PHY.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Paul Cercueil 2019-03-19 15:05:36 +01:00 committed by Stephen Boyd
parent 93dc07f8b0
commit eaa9558d35
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/ingenic/jz4725b-cgu.c
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@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
.mux = { CGU_REG_OPCR, 2, 1},
},
[JZ4725B_CLK_UDC_PHY] = {
"udc_phy", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_OPCR, 6, true },
},
};
static void __init jz4725b_cgu_init(struct device_node *np)