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dt-bindings: PCI: Add documentation for MediaTek PCIe
Add documentation for PCIe host driver available in MT7623 series SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
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Ryder Lee
Bjorn Helgaas
parent
637cfacae9
commit
ea7f4491e9
130
Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
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130
Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
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MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
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PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
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ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
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Required properties:
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- compatible: Should contain "mediatek,mt7623-pcie".
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- device_type: Must be "pci"
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- reg: Base addresses and lengths of the PCIe controller.
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- #address-cells: Address representation for root ports (must be 3)
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- #size-cells: Size representation for root ports (must be 2)
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- #interrupt-cells: Size representation for interrupts (must be 1)
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- free_ck :for reference clock of PCIe subsys
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- sys_ck0 :for clock of Port0
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- sys_ck1 :for clock of Port1
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- sys_ck2 :for clock of Port2
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- pcie-rst0 :port0 reset
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- pcie-rst1 :port1 reset
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- pcie-rst2 :port2 reset
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- phys: List of PHY specifiers (used by generic PHY framework).
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- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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- power-domains: A phandle and power domain specifier pair to the power domain
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which is responsible for collapsing and restoring power to the peripheral.
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- bus-range: Range of bus numbers associated with this controller.
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- ranges: Ranges for the PCI memory and I/O regions.
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In addition, the device tree node must have sub-nodes describing each
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PCIe port interface, having the following mandatory properties:
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Required properties:
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- device_type: Must be "pci"
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- reg: Only the first four bytes are used to refer to the correct bus number
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and device number.
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- #address-cells: Must be 3
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- #size-cells: Must be 2
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- #interrupt-cells: Must be 1
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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property is sufficient.
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- num-lanes: Number of lanes to use for this port.
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Examples:
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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"syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pcie: pcie-controller@1a140000 {
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compatible = "mediatek,mt7623-pcie";
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device_type = "pci";
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reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
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<0 0x1a142000 0 0x1000>, /* Port0 registers */
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<0 0x1a143000 0 0x1000>, /* Port1 registers */
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<0 0x1a144000 0 0x1000>; /* Port2 registers */
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 0>;
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interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
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<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
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<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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<&hifsys CLK_HIFSYS_PCIE0>,
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<&hifsys CLK_HIFSYS_PCIE1>,
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<&hifsys CLK_HIFSYS_PCIE2>;
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clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
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resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
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<&hifsys MT2701_HIFSYS_PCIE1_RST>,
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<&hifsys MT2701_HIFSYS_PCIE2_RST>;
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reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
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phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
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phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
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0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
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pcie@0,0 {
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device_type = "pci";
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@1,0 {
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device_type = "pci";
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@2,0 {
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device_type = "pci";
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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};
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