renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-21 19:53:59 +08:00
Code

ARM: pxa: define clock registers as __iomem

Browse Source 
We should not dereference registers as pointers, so use readl/writel
instead for these registers.

The clock registers are accessed in multiple files, so we have to
change them all at once.

I stumbled over these registers while looking at something unrelated.
There are in fact other registers with the same problem, but I did
not try to address those at this point.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
This commit is contained in:
Arnd Bergmann 2016-01-29 15:06:25 +01:00 committed by Robert Jarzmik
parent 92e963f50f
commit ea7743e271
8 changed files with 34 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-pxa/gumstix.c
View File

@ -139,14 +139,14 @@ static void gumstix_setup_bt_clock(void)
{ {
int timeout = 500; int timeout = 500;
if (!(OSCC & OSCC_OOK)) if (!(readl(OSCC) & OSCC_OOK))
pr_warn("32kHz clock was not on. Bootloader may need to be updated\n"); pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
else else
return; return;
OSCC |= OSCC_OON; writel(readl(OSCC) | OSCC_OON, OSCC);
do { do {
if (OSCC & OSCC_OOK) if (readl(OSCC) & OSCC_OOK)
break; break;
udelay(1); udelay(1);
} while (--timeout); } while (--timeout);

8
arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
View File

@ -134,10 +134,10 @@
/* /*
* PXA2xx specific Core clock definitions * PXA2xx specific Core clock definitions
*/ */
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */ #define CKEN io_p2v(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */

2
arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
View File

@ -18,7 +18,7 @@
/* /*
* Oscillator Configuration Register (OSCC) * Oscillator Configuration Register (OSCC)
*/ */
#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
#define OSCC_PEN (1 << 11) /* 13MHz POUT */ #define OSCC_PEN (1 << 11) /* 13MHz POUT */

2
arch/arm/mach-pxa/zeus.c
View File

@ -910,7 +910,7 @@ static void __init zeus_map_io(void)
PMCR = PSPR = 0; PMCR = PSPR = 0;
/* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */ /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
OSCC |= OSCC_OON; writel(readl(OSCC) | OSCC_OON, OSCC);
/* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...). /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
* float chip selects and PCMCIA */ * float chip selects and PCMCIA */

12
drivers/clk/pxa/clk-pxa25x.c
View File

@ -84,7 +84,7 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned long cccr = CCCR; unsigned long cccr = readl(CCCR);
unsigned int m = M_clk_mult[(cccr >> 5) & 0x03]; unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
return parent_rate / m; return parent_rate / m;
@ -99,7 +99,7 @@ PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
#define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
bit, is_lp, flags) \ bit, is_lp, flags) \
PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \ PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
is_lp, &CKEN, CKEN_ ## bit, flags) is_lp, CKEN, CKEN_ ## bit, flags)
#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \ PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
div_hp, bit, NULL, 0) div_hp, bit, NULL, 0)
@ -112,10 +112,10 @@ PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
&CKEN, CKEN_ ## bit, 0) CKEN, CKEN_ ## bit, 0)
#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
static struct desc_clk_cken pxa25x_clocks[] __initdata = { static struct desc_clk_cken pxa25x_clocks[] __initdata = {
PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0), PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
@ -162,7 +162,7 @@ MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw, static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned long cccr = CCCR; unsigned long cccr = readl(CCCR);
unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07]; unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
return (parent_rate / n2) * 2; return (parent_rate / n2) * 2;
@ -173,7 +173,7 @@ RATE_RO_OPS(clk_pxa25x_run, "run");
static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw, static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned long clkcfg, cccr = CCCR; unsigned long clkcfg, cccr = readl(CCCR);
unsigned int l, m, n2, t; unsigned int l, m, n2, t;
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));

34
drivers/clk/pxa/clk-pxa27x.c
View File

@ -85,7 +85,7 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
bool pxa27x_is_ppll_disabled(void) bool pxa27x_is_ppll_disabled(void)
{ {
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
return ccsr & (1 << CCCR_PPDIS_BIT); return ccsr & (1 << CCCR_PPDIS_BIT);
} }
@ -93,7 +93,7 @@ bool pxa27x_is_ppll_disabled(void)
#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
bit, is_lp, flags) \ bit, is_lp, flags) \
PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \ PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
is_lp, &CKEN, CKEN_ ## bit, flags) is_lp, CKEN, CKEN_ ## bit, flags)
#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \ PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
div_hp, bit, pxa27x_is_ppll_disabled, 0) div_hp, bit, pxa27x_is_ppll_disabled, 0)
@ -106,10 +106,10 @@ PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
&CKEN, CKEN_ ## bit, 0) CKEN, CKEN_ ## bit, 0)
#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
static struct desc_clk_cken pxa27x_clocks[] __initdata = { static struct desc_clk_cken pxa27x_clocks[] __initdata = {
PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1), PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
@ -151,7 +151,7 @@ static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
unsigned long clkcfg; unsigned long clkcfg;
unsigned int t, ht; unsigned int t, ht;
unsigned int l, L, n2, N; unsigned int l, L, n2, N;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
t = clkcfg & (1 << 0); t = clkcfg & (1 << 0);
@ -171,8 +171,8 @@ static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned int l, osc_forced; unsigned int l, osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
unsigned long cccr = CCCR; unsigned long cccr = readl(CCCR);
l = ccsr & CCSR_L_MASK; l = ccsr & CCSR_L_MASK;
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
@ -193,7 +193,7 @@ static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw) static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
{ {
unsigned int osc_forced; unsigned int osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
if (osc_forced) if (osc_forced)
@ -222,7 +222,7 @@ static unsigned long clk_pxa27x_core_get_rate(struct clk_hw *hw,
{ {
unsigned long clkcfg; unsigned long clkcfg;
unsigned int t, ht, b, osc_forced; unsigned int t, ht, b, osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
@ -242,7 +242,7 @@ static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
{ {
unsigned long clkcfg; unsigned long clkcfg;
unsigned int t, ht, b, osc_forced; unsigned int t, ht, b, osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
if (osc_forced) if (osc_forced)
@ -263,7 +263,7 @@ MUX_RO_RATE_RO_OPS(clk_pxa27x_core, "core");
static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw, static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
return (parent_rate / n2) * 2; return (parent_rate / n2) * 2;
@ -285,7 +285,7 @@ static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
{ {
unsigned long clkcfg; unsigned long clkcfg;
unsigned int b, osc_forced; unsigned int b, osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
@ -302,7 +302,7 @@ static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw) static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
{ {
unsigned int osc_forced; unsigned int osc_forced;
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
if (osc_forced) if (osc_forced)
@ -318,8 +318,8 @@ static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned int a, l, osc_forced; unsigned int a, l, osc_forced;
unsigned long cccr = CCCR; unsigned long cccr = readl(CCCR);
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
a = cccr & (1 << CCCR_A_BIT); a = cccr & (1 << CCCR_A_BIT);
@ -337,8 +337,8 @@ static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
{ {
unsigned int osc_forced, a; unsigned int osc_forced, a;
unsigned long cccr = CCCR; unsigned long cccr = readl(CCCR);
unsigned long ccsr = CCSR; unsigned long ccsr = readl(CCSR);
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
a = cccr & (1 << CCCR_A_BIT); a = cccr & (1 << CCCR_A_BIT);

3
drivers/clk/pxa/clk-pxa3xx.c
View File

@ -334,8 +334,7 @@ static void __init pxa3xx_base_clocks_init(void)
clk_register_clk_pxa3xx_system_bus(); clk_register_clk_pxa3xx_system_bus();
clk_register_clk_pxa3xx_ac97(); clk_register_clk_pxa3xx_ac97();
clk_register_clk_pxa3xx_smemc(); clk_register_clk_pxa3xx_smemc();
clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0, clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0, OSCC, 11, 0, NULL);
(void __iomem *)&OSCC, 11, 0, NULL);
clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL, clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
clk_register_fixed_factor(NULL, "os-timer0", clk_register_fixed_factor(NULL, "os-timer0",
"osc_13mhz", 0, 1, 4)); "osc_13mhz", 0, 1, 4));

2
drivers/cpufreq/pxa2xx-cpufreq.c
View File

@ -319,7 +319,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
local_irq_save(flags); local_irq_save(flags);
/* Set new the CCCR and prepare CCLKCFG */ /* Set new the CCCR and prepare CCLKCFG */
CCCR = pxa_freq_settings[idx].cccr; writel(pxa_freq_settings[idx].cccr, CCCR);
cclkcfg = pxa_freq_settings[idx].cclkcfg; cclkcfg = pxa_freq_settings[idx].cclkcfg;
asm volatile(" \n\ asm volatile(" \n\