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ioat: implement a private tx_list
Drop ioatdma's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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308136d1ab
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@ -251,12 +251,12 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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/* write address into NextDescriptor field of last desc in chain */
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/* write address into NextDescriptor field of last desc in chain */
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first = to_ioat_desc(tx->tx_list.next);
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first = to_ioat_desc(desc->tx_list.next);
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chain_tail = to_ioat_desc(ioat->used_desc.prev);
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chain_tail = to_ioat_desc(ioat->used_desc.prev);
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/* make descriptor updates globally visible before chaining */
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/* make descriptor updates globally visible before chaining */
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wmb();
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wmb();
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chain_tail->hw->next = first->txd.phys;
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chain_tail->hw->next = first->txd.phys;
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list_splice_tail_init(&tx->tx_list, &ioat->used_desc);
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list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
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dump_desc_dbg(ioat, chain_tail);
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dump_desc_dbg(ioat, chain_tail);
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dump_desc_dbg(ioat, first);
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dump_desc_dbg(ioat, first);
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@ -297,6 +297,7 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
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memset(desc, 0, sizeof(*desc));
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memset(desc, 0, sizeof(*desc));
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INIT_LIST_HEAD(&desc_sw->tx_list);
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dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
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dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
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desc_sw->txd.tx_submit = ioat1_tx_submit;
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desc_sw->txd.tx_submit = ioat1_tx_submit;
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desc_sw->hw = desc;
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desc_sw->hw = desc;
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@ -521,7 +522,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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desc->txd.flags = flags;
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desc->txd.flags = flags;
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desc->len = total_len;
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desc->len = total_len;
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list_splice(&chain, &desc->txd.tx_list);
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list_splice(&chain, &desc->tx_list);
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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hw->ctl_f.compl_write = 1;
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hw->tx_cnt = tx_cnt;
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hw->tx_cnt = tx_cnt;
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@ -157,7 +157,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor
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* @hw: hardware DMA descriptor
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* @node: this descriptor will either be on the free list,
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (async_tx.tx_list)
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* or attached to a transaction list (tx_list)
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* @txd: the generic software descriptor for all engines
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* @txd: the generic software descriptor for all engines
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* @id: identifier for debug
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* @id: identifier for debug
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*/
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*/
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@ -165,6 +165,7 @@ struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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struct list_head node;
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size_t len;
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size_t len;
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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struct dma_async_tx_descriptor txd;
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#ifdef DEBUG
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#ifdef DEBUG
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int id;
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int id;
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