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i2c-eg20t: add driver for Intel EG20T
I2C driver for Intel EG20T PCH Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Qi Wang <qi.wang@intel.com> [ben-linux@fluff.org: reworded commit message] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Tomoya MORINAGA
Ben Dooks
parent
03ed6a3aa6
commit
e9bc8fa5df
@ -638,6 +638,14 @@ config I2C_XILINX
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This driver can also be built as a module. If so, the module
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will be called xilinx_i2c.
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config I2C_EG20T
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tristate "PCH I2C of Intel EG20T"
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depends on PCI
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help
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This driver is for PCH(Platform controller Hub) I2C of EG20T which
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is an IOH(Input/Output Hub) for x86 embedded processor.
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This driver can access PCH I2C bus device.
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comment "External I2C/SMBus adapter drivers"
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config I2C_PARPORT
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@ -61,6 +61,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
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obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
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# External I2C/SMBus adapter drivers
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obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
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900
drivers/i2c/busses/i2c-eg20t.c
Normal file
900
drivers/i2c/busses/i2c-eg20t.c
Normal file
@ -0,0 +1,900 @@
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/*
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* Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/ktime.h>
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#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
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#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
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#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
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#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
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#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
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#define PCH_I2CSADR 0x00 /* I2C slave address register */
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#define PCH_I2CCTL 0x04 /* I2C control register */
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#define PCH_I2CSR 0x08 /* I2C status register */
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#define PCH_I2CDR 0x0C /* I2C data register */
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#define PCH_I2CMON 0x10 /* I2C bus monitor register */
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#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
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#define PCH_I2CMOD 0x18 /* I2C mode register */
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#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
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#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
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#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
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#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
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#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
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#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
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#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
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#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
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#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
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#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
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#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
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#define PCH_I2CTMR 0x48 /* I2C timer register */
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#define PCH_I2CSRST 0xFC /* I2C reset register */
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#define PCH_I2CNF 0xF8 /* I2C noise filter register */
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#define BUS_IDLE_TIMEOUT 20
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#define PCH_I2CCTL_I2CMEN 0x0080
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#define TEN_BIT_ADDR_DEFAULT 0xF000
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#define TEN_BIT_ADDR_MASK 0xF0
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#define PCH_START 0x0020
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#define PCH_ESR_START 0x0001
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#define PCH_BUFF_START 0x1
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#define PCH_REPSTART 0x0004
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#define PCH_ACK 0x0008
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#define PCH_GETACK 0x0001
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#define CLR_REG 0x0
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#define I2C_RD 0x1
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#define I2CMCF_BIT 0x0080
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#define I2CMIF_BIT 0x0002
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#define I2CMAL_BIT 0x0010
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#define I2CBMFI_BIT 0x0001
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#define I2CBMAL_BIT 0x0002
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#define I2CBMNA_BIT 0x0004
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#define I2CBMTO_BIT 0x0008
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#define I2CBMIS_BIT 0x0010
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#define I2CESRFI_BIT 0X0001
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#define I2CESRTO_BIT 0x0002
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#define I2CESRFIIE_BIT 0x1
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#define I2CESRTOIE_BIT 0x2
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#define I2CBMDZ_BIT 0x0040
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#define I2CBMAG_BIT 0x0020
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#define I2CMBB_BIT 0x0020
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#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
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I2CBMTO_BIT | I2CBMIS_BIT)
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#define I2C_ADDR_MSK 0xFF
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#define I2C_MSB_2B_MSK 0x300
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#define FAST_MODE_CLK 400
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#define FAST_MODE_EN 0x0001
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#define SUB_ADDR_LEN_MAX 4
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#define BUF_LEN_MAX 32
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#define PCH_BUFFER_MODE 0x1
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#define EEPROM_SW_RST_MODE 0x0002
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#define NORMAL_INTR_ENBL 0x0300
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#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
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#define EEPROM_RST_INTR_DISBL 0x0
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#define BUFFER_MODE_INTR_ENBL 0x001F
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#define BUFFER_MODE_INTR_DISBL 0x0
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#define NORMAL_MODE 0x0
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#define BUFFER_MODE 0x1
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#define EEPROM_SR_MODE 0x2
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#define I2C_TX_MODE 0x0010
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#define PCH_BUF_TX 0xFFF7
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#define PCH_BUF_RD 0x0008
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#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
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I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
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#define I2CMAL_EVENT 0x0001
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#define I2CMCF_EVENT 0x0002
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#define I2CBMFI_EVENT 0x0004
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#define I2CBMAL_EVENT 0x0008
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#define I2CBMNA_EVENT 0x0010
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#define I2CBMTO_EVENT 0x0020
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#define I2CBMIS_EVENT 0x0040
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#define I2CESRFI_EVENT 0x0080
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#define I2CESRTO_EVENT 0x0100
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#define PCI_DEVICE_ID_PCH_I2C 0x8817
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#define pch_dbg(adap, fmt, arg...) \
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dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
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#define pch_err(adap, fmt, arg...) \
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dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
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#define pch_pci_err(pdev, fmt, arg...) \
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dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
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#define pch_pci_dbg(pdev, fmt, arg...) \
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dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
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/**
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* struct i2c_algo_pch_data - for I2C driver functionalities
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* @pch_adapter: stores the reference to i2c_adapter structure
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* @p_adapter_info: stores the reference to adapter_info structure
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* @pch_base_address: specifies the remapped base address
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* @pch_buff_mode_en: specifies if buffer mode is enabled
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* @pch_event_flag: specifies occurrence of interrupt events
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* @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
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*/
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struct i2c_algo_pch_data {
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struct i2c_adapter pch_adapter;
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struct adapter_info *p_adapter_info;
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void __iomem *pch_base_address;
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int pch_buff_mode_en;
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u32 pch_event_flag;
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bool pch_i2c_xfer_in_progress;
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};
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/**
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* struct adapter_info - This structure holds the adapter information for the
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PCH i2c controller
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* @pch_data: stores a list of i2c_algo_pch_data
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* @pch_i2c_suspended: specifies whether the system is suspended or not
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* perhaps with more lines and words.
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*
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* pch_data has as many elements as maximum I2C channels
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*/
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struct adapter_info {
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struct i2c_algo_pch_data pch_data;
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bool pch_i2c_suspended;
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};
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static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
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static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
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static wait_queue_head_t pch_event;
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static DEFINE_MUTEX(pch_mutex);
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static struct pci_device_id __devinitdata pch_pcidev_id[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
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{0,}
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};
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static irqreturn_t pch_i2c_handler(int irq, void *pData);
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static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
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{
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u32 val;
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val = ioread32(addr + offset);
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val |= bitmask;
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iowrite32(val, addr + offset);
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}
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static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
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{
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u32 val;
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val = ioread32(addr + offset);
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val &= (~bitmask);
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iowrite32(val, addr + offset);
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}
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/**
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* pch_i2c_init() - hardware initialization of I2C module
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* @adap: Pointer to struct i2c_algo_pch_data.
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*/
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static void pch_i2c_init(struct i2c_algo_pch_data *adap)
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{
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void __iomem *p = adap->pch_base_address;
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u32 pch_i2cbc;
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u32 pch_i2ctmr;
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u32 reg_value;
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/* reset I2C controller */
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iowrite32(0x01, p + PCH_I2CSRST);
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msleep(20);
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iowrite32(0x0, p + PCH_I2CSRST);
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/* Initialize I2C registers */
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iowrite32(0x21, p + PCH_I2CNF);
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pch_setbit(adap->pch_base_address, PCH_I2CCTL,
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PCH_I2CCTL_I2CMEN);
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if (pch_i2c_speed != 400)
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pch_i2c_speed = 100;
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reg_value = PCH_I2CCTL_I2CMEN;
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if (pch_i2c_speed == FAST_MODE_CLK) {
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reg_value |= FAST_MODE_EN;
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pch_dbg(adap, "Fast mode enabled\n");
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}
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if (pch_clk > PCH_MAX_CLK)
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pch_clk = 62500;
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pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
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/* Set transfer speed in I2CBC */
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iowrite32(pch_i2cbc, p + PCH_I2CBC);
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pch_i2ctmr = (pch_clk) / 8;
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iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
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reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
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iowrite32(reg_value, p + PCH_I2CCTL);
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pch_dbg(adap,
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"I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
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ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
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init_waitqueue_head(&pch_event);
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}
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static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
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{
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return cmp1.tv64 < cmp2.tv64;
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}
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/**
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* pch_i2c_wait_for_bus_idle() - check the status of bus.
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* @adap: Pointer to struct i2c_algo_pch_data.
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* @timeout: waiting time counter (us).
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*/
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static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
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s32 timeout)
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{
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void __iomem *p = adap->pch_base_address;
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/* MAX timeout value is timeout*1000*1000nsec */
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ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
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do {
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if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
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break;
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msleep(20);
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} while (ktime_lt(ktime_get(), ns_val));
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pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
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if (timeout == 0) {
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pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
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return -ETIME;
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}
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return 0;
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}
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/**
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* pch_i2c_start() - Generate I2C start condition in normal mode.
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* @adap: Pointer to struct i2c_algo_pch_data.
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*
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* Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
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*/
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static void pch_i2c_start(struct i2c_algo_pch_data *adap)
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{
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void __iomem *p = adap->pch_base_address;
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pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
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pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
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}
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/**
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* pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
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* @adap: Pointer to struct i2c_algo_pch_data.
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*/
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static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
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{
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s32 ret;
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ret = wait_event_timeout(pch_event,
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(adap->pch_event_flag != 0), msecs_to_jiffies(50));
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if (ret < 0) {
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pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
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return ret;
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}
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if (ret == 0) {
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pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
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return -ETIMEDOUT;
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}
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if (adap->pch_event_flag & I2C_ERROR_MASK) {
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pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
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return -EIO;
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}
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adap->pch_event_flag = 0;
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return 0;
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}
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/**
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* pch_i2c_getack() - to confirm ACK/NACK
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* @adap: Pointer to struct i2c_algo_pch_data.
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*/
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static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
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{
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u32 reg_val;
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void __iomem *p = adap->pch_base_address;
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reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
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if (reg_val != 0) {
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pch_err(adap, "return%d\n", -EPROTO);
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return -EPROTO;
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}
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return 0;
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}
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/**
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* pch_i2c_stop() - generate stop condition in normal mode.
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* @adap: Pointer to struct i2c_algo_pch_data.
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*/
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static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
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{
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void __iomem *p = adap->pch_base_address;
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pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
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/* clear the start bit */
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pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
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}
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/**
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* pch_i2c_repstart() - generate repeated start condition in normal mode
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* @adap: Pointer to struct i2c_algo_pch_data.
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*/
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static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
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{
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void __iomem *p = adap->pch_base_address;
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pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
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pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
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}
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/**
|
||||
* pch_i2c_writebytes() - write data to I2C bus in normal mode
|
||||
* @i2c_adap: Pointer to the struct i2c_adapter.
|
||||
* @last: specifies whether last message or not.
|
||||
* In the case of compound mode it will be 1 for last message,
|
||||
* otherwise 0.
|
||||
* @first: specifies whether first message or not.
|
||||
* 1 for first message otherwise 0.
|
||||
*/
|
||||
static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
|
||||
struct i2c_msg *msgs, u32 last, u32 first)
|
||||
{
|
||||
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
|
||||
u8 *buf;
|
||||
u32 length;
|
||||
u32 addr;
|
||||
u32 addr_2_msb;
|
||||
u32 addr_8_lsb;
|
||||
s32 wrcount;
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
|
||||
length = msgs->len;
|
||||
buf = msgs->buf;
|
||||
addr = msgs->addr;
|
||||
|
||||
/* enable master tx */
|
||||
pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
|
||||
|
||||
pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
|
||||
length);
|
||||
|
||||
if (first) {
|
||||
if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
if (msgs->flags & I2C_M_TEN) {
|
||||
addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
|
||||
iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
|
||||
if (first)
|
||||
pch_i2c_start(adap);
|
||||
if (pch_i2c_wait_for_xfer_complete(adap) == 0 &&
|
||||
pch_i2c_getack(adap) == 0) {
|
||||
addr_8_lsb = (addr & I2C_ADDR_MSK);
|
||||
iowrite32(addr_8_lsb, p + PCH_I2CDR);
|
||||
} else {
|
||||
pch_i2c_stop(adap);
|
||||
return -ETIME;
|
||||
}
|
||||
} else {
|
||||
/* set 7 bit slave address and R/W bit as 0 */
|
||||
iowrite32(addr << 1, p + PCH_I2CDR);
|
||||
if (first)
|
||||
pch_i2c_start(adap);
|
||||
}
|
||||
|
||||
if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
|
||||
(pch_i2c_getack(adap) == 0)) {
|
||||
for (wrcount = 0; wrcount < length; ++wrcount) {
|
||||
/* write buffer value to I2C data register */
|
||||
iowrite32(buf[wrcount], p + PCH_I2CDR);
|
||||
pch_dbg(adap, "writing %x to Data register\n",
|
||||
buf[wrcount]);
|
||||
|
||||
if (pch_i2c_wait_for_xfer_complete(adap) != 0)
|
||||
return -ETIME;
|
||||
|
||||
if (pch_i2c_getack(adap))
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* check if this is the last message */
|
||||
if (last)
|
||||
pch_i2c_stop(adap);
|
||||
else
|
||||
pch_i2c_repstart(adap);
|
||||
} else {
|
||||
pch_i2c_stop(adap);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
pch_dbg(adap, "return=%d\n", wrcount);
|
||||
|
||||
return wrcount;
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_sendack() - send ACK
|
||||
* @adap: Pointer to struct i2c_algo_pch_data.
|
||||
*/
|
||||
static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
|
||||
{
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
|
||||
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_sendnack() - send NACK
|
||||
* @adap: Pointer to struct i2c_algo_pch_data.
|
||||
*/
|
||||
static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
|
||||
{
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
|
||||
pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_readbytes() - read data from I2C bus in normal mode.
|
||||
* @i2c_adap: Pointer to the struct i2c_adapter.
|
||||
* @msgs: Pointer to i2c_msg structure.
|
||||
* @last: specifies whether last message or not.
|
||||
* @first: specifies whether first message or not.
|
||||
*/
|
||||
s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
|
||||
u32 last, u32 first)
|
||||
{
|
||||
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
|
||||
|
||||
u8 *buf;
|
||||
u32 count;
|
||||
u32 length;
|
||||
u32 addr;
|
||||
u32 addr_2_msb;
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
|
||||
length = msgs->len;
|
||||
buf = msgs->buf;
|
||||
addr = msgs->addr;
|
||||
|
||||
/* enable master reception */
|
||||
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
|
||||
|
||||
if (first) {
|
||||
if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
if (msgs->flags & I2C_M_TEN) {
|
||||
addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
|
||||
iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
|
||||
|
||||
} else {
|
||||
/* 7 address bits + R/W bit */
|
||||
addr = (((addr) << 1) | (I2C_RD));
|
||||
iowrite32(addr, p + PCH_I2CDR);
|
||||
}
|
||||
|
||||
/* check if it is the first message */
|
||||
if (first)
|
||||
pch_i2c_start(adap);
|
||||
|
||||
if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
|
||||
(pch_i2c_getack(adap) == 0)) {
|
||||
pch_dbg(adap, "return %d\n", 0);
|
||||
|
||||
if (length == 0) {
|
||||
pch_i2c_stop(adap);
|
||||
ioread32(p + PCH_I2CDR); /* Dummy read needs */
|
||||
|
||||
count = length;
|
||||
} else {
|
||||
int read_index;
|
||||
int loop;
|
||||
pch_i2c_sendack(adap);
|
||||
|
||||
/* Dummy read */
|
||||
for (loop = 1, read_index = 0; loop < length; loop++) {
|
||||
buf[read_index] = ioread32(p + PCH_I2CDR);
|
||||
|
||||
if (loop != 1)
|
||||
read_index++;
|
||||
|
||||
if (pch_i2c_wait_for_xfer_complete(adap) != 0) {
|
||||
pch_i2c_stop(adap);
|
||||
return -ETIME;
|
||||
}
|
||||
} /* end for */
|
||||
|
||||
pch_i2c_sendnack(adap);
|
||||
|
||||
buf[read_index] = ioread32(p + PCH_I2CDR);
|
||||
|
||||
if (length != 1)
|
||||
read_index++;
|
||||
|
||||
if (pch_i2c_wait_for_xfer_complete(adap) == 0) {
|
||||
if (last)
|
||||
pch_i2c_stop(adap);
|
||||
else
|
||||
pch_i2c_repstart(adap);
|
||||
|
||||
buf[read_index++] = ioread32(p + PCH_I2CDR);
|
||||
count = read_index;
|
||||
} else {
|
||||
count = -ETIME;
|
||||
}
|
||||
|
||||
}
|
||||
} else {
|
||||
count = -ETIME;
|
||||
pch_i2c_stop(adap);
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_cb_ch0() - Interrupt handler Call back function
|
||||
* @adap: Pointer to struct i2c_algo_pch_data.
|
||||
*/
|
||||
static void pch_i2c_cb_ch0(struct i2c_algo_pch_data *adap)
|
||||
{
|
||||
u32 sts;
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
|
||||
sts = ioread32(p + PCH_I2CSR);
|
||||
sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
|
||||
if (sts & I2CMAL_BIT)
|
||||
adap->pch_event_flag |= I2CMAL_EVENT;
|
||||
|
||||
if (sts & I2CMCF_BIT)
|
||||
adap->pch_event_flag |= I2CMCF_EVENT;
|
||||
|
||||
/* clear the applicable bits */
|
||||
pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
|
||||
|
||||
pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
|
||||
|
||||
wake_up(&pch_event);
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_handler() - interrupt handler for the PCH I2C controller
|
||||
* @irq: irq number.
|
||||
* @pData: cookie passed back to the handler function.
|
||||
*/
|
||||
static irqreturn_t pch_i2c_handler(int irq, void *pData)
|
||||
{
|
||||
s32 reg_val;
|
||||
|
||||
struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
|
||||
void __iomem *p = adap_data->pch_base_address;
|
||||
u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
|
||||
|
||||
if (mode != NORMAL_MODE) {
|
||||
pch_err(adap_data, "I2C mode is not supported\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
reg_val = ioread32(p + PCH_I2CSR);
|
||||
if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
|
||||
pch_i2c_cb_ch0(adap_data);
|
||||
else
|
||||
return IRQ_NONE;
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_xfer() - Reading adnd writing data through I2C bus
|
||||
* @i2c_adap: Pointer to the struct i2c_adapter.
|
||||
* @msgs: Pointer to i2c_msg structure.
|
||||
* @num: number of messages.
|
||||
*/
|
||||
static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
|
||||
struct i2c_msg *msgs, s32 num)
|
||||
{
|
||||
struct i2c_msg *pmsg;
|
||||
u32 i = 0;
|
||||
u32 status;
|
||||
u32 msglen;
|
||||
u32 subaddrlen;
|
||||
s32 ret;
|
||||
|
||||
struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
|
||||
|
||||
ret = mutex_lock_interruptible(&pch_mutex);
|
||||
if (ret)
|
||||
return -ERESTARTSYS;
|
||||
|
||||
if (adap->p_adapter_info->pch_i2c_suspended) {
|
||||
mutex_unlock(&pch_mutex);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
|
||||
adap->p_adapter_info->pch_i2c_suspended);
|
||||
/* transfer not completed */
|
||||
adap->pch_i2c_xfer_in_progress = true;
|
||||
|
||||
pmsg = &msgs[0];
|
||||
pmsg->flags |= adap->pch_buff_mode_en;
|
||||
status = pmsg->flags;
|
||||
pch_dbg(adap,
|
||||
"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
|
||||
/* calculate sub address length and message length */
|
||||
/* these are applicable only for buffer mode */
|
||||
subaddrlen = pmsg->buf[0];
|
||||
/* calculate actual message length excluding
|
||||
* the sub address fields */
|
||||
msglen = (pmsg->len) - (subaddrlen + 1);
|
||||
if (status & (I2C_M_RD)) {
|
||||
pch_dbg(adap, "invoking pch_i2c_readbytes\n");
|
||||
ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
|
||||
(i == 0));
|
||||
} else {
|
||||
pch_dbg(adap, "invoking pch_i2c_writebytes\n");
|
||||
ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
|
||||
(i == 0));
|
||||
}
|
||||
|
||||
adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
|
||||
|
||||
mutex_unlock(&pch_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* pch_i2c_func() - return the functionality of the I2C driver
|
||||
* @adap: Pointer to struct i2c_algo_pch_data.
|
||||
*/
|
||||
static u32 pch_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm pch_algorithm = {
|
||||
.master_xfer = pch_i2c_xfer,
|
||||
.functionality = pch_i2c_func
|
||||
};
|
||||
|
||||
/**
|
||||
* pch_i2c_disbl_int() - Disable PCH I2C interrupts
|
||||
* @adap: Pointer to struct i2c_algo_pch_data.
|
||||
*/
|
||||
static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
|
||||
{
|
||||
void __iomem *p = adap->pch_base_address;
|
||||
|
||||
pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
|
||||
|
||||
iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
|
||||
|
||||
iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
|
||||
}
|
||||
|
||||
static int __devinit pch_i2c_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
void __iomem *base_addr;
|
||||
s32 ret;
|
||||
struct adapter_info *adap_info;
|
||||
|
||||
pch_pci_dbg(pdev, "Entered.\n");
|
||||
|
||||
adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
|
||||
if (adap_info == NULL) {
|
||||
pch_pci_err(pdev, "Memory allocation FAILED\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret) {
|
||||
pch_pci_err(pdev, "pci_enable_device FAILED\n");
|
||||
goto err_pci_enable;
|
||||
}
|
||||
|
||||
ret = pci_request_regions(pdev, KBUILD_MODNAME);
|
||||
if (ret) {
|
||||
pch_pci_err(pdev, "pci_request_regions FAILED\n");
|
||||
goto err_pci_req;
|
||||
}
|
||||
|
||||
base_addr = pci_iomap(pdev, 1, 0);
|
||||
|
||||
if (base_addr == NULL) {
|
||||
pch_pci_err(pdev, "pci_iomap FAILED\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_pci_iomap;
|
||||
}
|
||||
|
||||
adap_info->pch_i2c_suspended = false;
|
||||
|
||||
adap_info->pch_data.p_adapter_info = adap_info;
|
||||
|
||||
adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
|
||||
adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
|
||||
strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
|
||||
adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
|
||||
adap_info->pch_data.pch_adapter.algo_data =
|
||||
&adap_info->pch_data;
|
||||
|
||||
/* (i * 0x80) + base_addr; */
|
||||
adap_info->pch_data.pch_base_address = base_addr;
|
||||
|
||||
adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
|
||||
|
||||
ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
|
||||
|
||||
if (ret) {
|
||||
pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
|
||||
goto err_i2c_add_adapter;
|
||||
}
|
||||
|
||||
pch_i2c_init(&adap_info->pch_data);
|
||||
ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
|
||||
KBUILD_MODNAME, &adap_info->pch_data);
|
||||
if (ret) {
|
||||
pch_pci_err(pdev, "request_irq FAILED\n");
|
||||
goto err_request_irq;
|
||||
}
|
||||
|
||||
pci_set_drvdata(pdev, adap_info);
|
||||
pch_pci_dbg(pdev, "returns %d.\n", ret);
|
||||
return 0;
|
||||
|
||||
err_request_irq:
|
||||
i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
|
||||
err_i2c_add_adapter:
|
||||
pci_iounmap(pdev, base_addr);
|
||||
err_pci_iomap:
|
||||
pci_release_regions(pdev);
|
||||
err_pci_req:
|
||||
pci_disable_device(pdev);
|
||||
err_pci_enable:
|
||||
kfree(adap_info);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __devexit pch_i2c_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct adapter_info *adap_info = pci_get_drvdata(pdev);
|
||||
|
||||
pch_i2c_disbl_int(&adap_info->pch_data);
|
||||
free_irq(pdev->irq, &adap_info->pch_data);
|
||||
i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
|
||||
|
||||
if (adap_info->pch_data.pch_base_address) {
|
||||
pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
|
||||
adap_info->pch_data.pch_base_address = 0;
|
||||
}
|
||||
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
|
||||
pci_release_regions(pdev);
|
||||
|
||||
pci_disable_device(pdev);
|
||||
kfree(adap_info);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
{
|
||||
int ret;
|
||||
struct adapter_info *adap_info = pci_get_drvdata(pdev);
|
||||
void __iomem *p = adap_info->pch_data.pch_base_address;
|
||||
|
||||
adap_info->pch_i2c_suspended = true;
|
||||
|
||||
while ((adap_info->pch_data.pch_i2c_xfer_in_progress)) {
|
||||
/* Wait until all channel transfers are completed */
|
||||
msleep(20);
|
||||
}
|
||||
/* Disable the i2c interrupts */
|
||||
pch_i2c_disbl_int(&adap_info->pch_data);
|
||||
|
||||
pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
|
||||
"invoked function pch_i2c_disbl_int successfully\n",
|
||||
ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
|
||||
ioread32(p + PCH_I2CESRSTA));
|
||||
|
||||
ret = pci_save_state(pdev);
|
||||
|
||||
if (ret) {
|
||||
pch_pci_err(pdev, "pci_save_state\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pci_enable_wake(pdev, PCI_D3hot, 0);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pch_i2c_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct adapter_info *adap_info = pci_get_drvdata(pdev);
|
||||
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
|
||||
if (pci_enable_device(pdev) < 0) {
|
||||
pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
pci_enable_wake(pdev, PCI_D3hot, 0);
|
||||
|
||||
pch_i2c_init(&adap_info->pch_data);
|
||||
|
||||
adap_info->pch_i2c_suspended = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define pch_i2c_suspend NULL
|
||||
#define pch_i2c_resume NULL
|
||||
#endif
|
||||
|
||||
static struct pci_driver pch_pcidriver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = pch_pcidev_id,
|
||||
.probe = pch_i2c_probe,
|
||||
.remove = __devexit_p(pch_i2c_remove),
|
||||
.suspend = pch_i2c_suspend,
|
||||
.resume = pch_i2c_resume
|
||||
};
|
||||
|
||||
static int __init pch_pci_init(void)
|
||||
{
|
||||
return pci_register_driver(&pch_pcidriver);
|
||||
}
|
||||
module_init(pch_pci_init);
|
||||
|
||||
static void __exit pch_pci_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&pch_pcidriver);
|
||||
}
|
||||
module_exit(pch_pci_exit);
|
||||
|
||||
MODULE_DESCRIPTION("PCH I2C PCI Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
|
||||
module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
|
||||
module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
|
||||
Loading…
Reference in New Issue
Block a user