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powerpc: Add support for early tlbilx opcode
During the ISA 2.06 development the opcode for tlbilx changed and some early implementations used to old opcode. Add support for a MMU_FTR fixup to deal with this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -52,6 +52,12 @@
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*/
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#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
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/* This indicates that the processor uses the wrong opcode for tlbilx
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* instructions. During the ISA 2.06 development the opcode for tlbilx
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* changed and some early implementations used to old opcode
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*/
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#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000)
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#ifndef __ASSEMBLY__
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#include <asm/cputable.h>
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@ -44,6 +44,7 @@
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#define PPC_INST_STSWI 0x7c0005aa
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#define PPC_INST_STSWX 0x7c00052a
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#define PPC_INST_TLBILX 0x7c000024
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#define PPC_INST_TLBILX_EARLY 0x7c000626
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#define PPC_INST_WAIT 0x7c00007c
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/* macros to insert fields into opcodes */
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@ -63,10 +64,18 @@
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#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
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#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
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#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
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__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
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__PPC_T_TLB(t) | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
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#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
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#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
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#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \
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__PPC_T_TLB(t) | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b)
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#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b)
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#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b)
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#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
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__PPC_WC(w))
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@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_features = CPU_FTRS_E500MC,
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.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
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.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
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MMU_FTR_USE_TLBILX,
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MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE,
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.icache_bsize = 64,
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.dcache_bsize = 64,
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.num_pmcs = 4,
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@ -138,7 +138,11 @@ BEGIN_MMU_FTR_SECTION
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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MMU_FTR_SECTION_ELSE
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PPC_TLBILX_ALL(0,0)
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BEGIN_MMU_FTR_SECTION_NESTED(96)
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PPC_TLBILX_ALL(0,r3)
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MMU_FTR_SECTION_ELSE_NESTED(96)
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PPC_TLBILX_ALL_EARLY(0,r3)
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ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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@ -151,7 +155,11 @@ BEGIN_MMU_FTR_SECTION
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wrteei 0
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mfspr r4,SPRN_MAS6 /* save MAS6 */
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mtspr SPRN_MAS6,r3
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BEGIN_MMU_FTR_SECTION_NESTED(96)
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PPC_TLBILX_PID(0,0)
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MMU_FTR_SECTION_ELSE_NESTED(96)
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PPC_TLBILX_PID_EARLY(0,0)
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ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
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mtspr SPRN_MAS6,r4 /* restore MAS6 */
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wrtee r10
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MMU_FTR_SECTION_ELSE
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@ -185,7 +193,11 @@ BEGIN_MMU_FTR_SECTION
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mtspr SPRN_MAS1,r4
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tlbwe
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MMU_FTR_SECTION_ELSE
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BEGIN_MMU_FTR_SECTION_NESTED(96)
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PPC_TLBILX_VA(0,r3)
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MMU_FTR_SECTION_ELSE_NESTED(96)
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PPC_TLBILX_VA_EARLY(0,r3)
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ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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