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spi: STIG Mode Fixes for spi-cadence-qspi driver
Merge series from Dhruva Gole <d-gole@ti.com>: * Reset the CMD_CTRL Register, without which read/writes in STIG mode were failing in some cases. The issue came to light while using STIG Mode for small reads. * Also add a flag that can allow us to do direct reads but distinguish direct writes, thus enabling us to disable writes in DAC mode in some cases that require it. (Like to write to some connected Flash registers) * Fix register reads in STIG mode and also use STIG mode while reading flash registers. Currently if you try to read a register while in STIG mode there is no support for ADDR and thus naturally a register never gets read from the flash. This patch series has been tested on a TI AM625-SK-EVM with both a quad spi nor flash (s25hs) and OSPI NOR Flash (s28hs). Output of ltp-ddt test, "DD_RW_ERASESIZE_UBIFS" run with s25hs512t flash: ... [ 2.334068] spi-nor spi0.0: s25hs512t (65536 Kbytes) [ 2.339185] 7 fixed-partitions partitions found on MTD device fc40000.spi.0 [ 2.346158] Creating 7 MTD partitions on "fc40000.spi.0": [ 2.351555] 0x000000000000-0x000000080000 : "ospi.tiboot3" [ 2.358344] 0x000000080000-0x000000280000 : "ospi.tispl" [ 2.364788] 0x000000280000-0x000000680000 : "ospi.u-boot" [ 2.371311] 0x000000680000-0x0000006c0000 : "ospi.env" [ 2.377519] 0x0000006c0000-0x000000700000 : "ospi.env.backup" [ 2.384419] 0x000000800000-0x000003fc0000 : "ospi.rootfs" [ 2.390890] 0x000003fc0000-0x000004000000 : "ospi.phypattern" ..snip.. Test Start Time: Wed Jan 11 21:14:31 2023 ----------------------------------------- Testcase Result Exit Value -------- ------ ---------- OSPI_S_FUNC_DD_RW_ERASESIZE_UBIFS PASS 0 ----------------------------------------------- Total Tests: 1 Total Skipped Tests: 0 Total Failures: 0 Kernel Version: 6.2.0-rc1-00040-g700d796a94e0-dirty Machine Architecture: aarch64 Hostname: am62xx-evm
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commit
e976222544
@ -84,6 +84,7 @@ struct cqspi_st {
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u32 trigger_address;
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u32 wr_delay;
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bool use_direct_mode;
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bool use_direct_mode_wr;
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struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
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bool use_dma_read;
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u32 pd_dev_id;
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@ -531,6 +532,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
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/* 0 means 1 byte. */
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reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
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<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
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/* setup ADDR BIT field */
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if (op->addr.nbytes) {
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reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
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reg |= ((op->addr.nbytes - 1) &
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CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
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<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
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writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
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}
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status = cqspi_exec_flash_cmd(cqspi, reg);
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if (status)
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return status;
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@ -549,6 +561,9 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
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memcpy(rxbuf, ®, read_len);
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}
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/* Reset CMD_CTRL Reg once command read completes */
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writel(0, reg_base + CQSPI_REG_CMDCTRL);
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return 0;
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}
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@ -613,7 +628,12 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
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}
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}
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return cqspi_exec_flash_cmd(cqspi, reg);
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ret = cqspi_exec_flash_cmd(cqspi, reg);
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/* Reset CMD_CTRL Reg once command write completes */
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writel(0, reg_base + CQSPI_REG_CMDCTRL);
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return ret;
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}
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static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
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@ -937,6 +957,12 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
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reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
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writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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/*
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* DAC mode require auto polling as flash needs to be polled
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* for write completion in case of bubble in SPI transaction
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* due to slow CPU/DMA master.
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*/
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cqspi->use_direct_mode_wr = false;
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}
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reg = readl(reg_base + CQSPI_REG_SIZE);
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@ -1222,7 +1248,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
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* data.
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*/
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if (!op->cmd.dtr && cqspi->use_direct_mode &&
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((to + len) <= cqspi->ahb_size)) {
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cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
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memcpy_toio(cqspi->ahb_base + to, buf, len);
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return cqspi_wait_idle(cqspi);
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}
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@ -1333,7 +1359,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
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cqspi_configure(f_pdata, mem->spi->max_speed_hz);
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if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
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if (!op->addr.nbytes)
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/*
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* Performing reads in DAC mode forces to read minimum 4 bytes
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* which is unsupported on some flash devices during register
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* reads, prefer STIG mode for such small reads.
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*/
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if (!op->addr.nbytes ||
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op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
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return cqspi_command_read(f_pdata, op);
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return cqspi_read(f_pdata, op);
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@ -1692,8 +1724,10 @@ static int cqspi_probe(struct platform_device *pdev)
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cqspi->master_ref_clk_hz);
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if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
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master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
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if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
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if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
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cqspi->use_direct_mode = true;
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cqspi->use_direct_mode_wr = true;
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}
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if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
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cqspi->use_dma_read = true;
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if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
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