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rt2x00: Fix rt2800 txpower setting to correct value
TX_PWR_CFG_* setting need to consider below cases -compesate 20M/40M tx power delta for 2.4/5GHZ band -limit maximum EIRP tx power to power_level of regulatory requirement Signed-off-by: RA-Jay Hung <jay_hung@ralinktech.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
RA-Jay Hung
John W. Linville
parent
d96aa64096
commit
e90c54b235
@ -1703,11 +1703,14 @@ struct mac_iveiv_entry {
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*/
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/*
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* BBP 1: TX Antenna & Power
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* POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
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* 3 - increase tx power by 6dBm
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* BBP 1: TX Antenna & Power Control
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* POWER_CTRL:
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* 0 - normal,
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* 1 - drop tx power by 6dBm,
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* 2 - drop tx power by 12dBm,
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* 3 - increase tx power by 6dBm
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*/
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#define BBP1_TX_POWER FIELD8(0x07)
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#define BBP1_TX_POWER_CTRL FIELD8(0x07)
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#define BBP1_TX_ANTENNA FIELD8(0x18)
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/*
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@ -2001,23 +2004,26 @@ struct mac_iveiv_entry {
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#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
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/*
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* EEPROM Maximum TX power values
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* EEPROM EIRP Maximum TX power values(unit: dbm)
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*/
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#define EEPROM_MAX_TX_POWER 0x0027
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#define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff)
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#define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00)
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#define EEPROM_EIRP_MAX_TX_POWER 0x0027
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#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
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#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
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/*
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* EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
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* This is delta in 40MHZ.
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* VALUE: Tx Power dalta value (MAX=4)
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* VALUE: Tx Power dalta value, MAX=4(unit: dbm)
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* TYPE: 1: Plus the delta value, 0: minus the delta value
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* TXPOWER: Enable:
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* ENABLE: enable tx power compensation for 40BW
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*/
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#define EEPROM_TXPOWER_DELTA 0x0028
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#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
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#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
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#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
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#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
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#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
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#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
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#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
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#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
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#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
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/*
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* EEPROM TXPOWER 802.11BG
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@ -2215,4 +2221,9 @@ struct mac_iveiv_entry {
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#define TXPOWER_A_TO_DEV(__txpower) \
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clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
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/*
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* Board's maximun TX power limitation
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*/
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#define EIRP_MAX_TX_POWER_LIMIT 0x50
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#endif /* RT2800_H */
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@ -1684,30 +1684,116 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
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rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®);
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}
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static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
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enum ieee80211_band band)
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{
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u16 eeprom;
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u8 comp_en;
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u8 comp_type;
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int comp_value;
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rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
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if (eeprom == 0xffff)
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return 0;
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if (band == IEEE80211_BAND_2GHZ) {
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comp_en = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_ENABLE_2G);
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if (comp_en) {
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comp_type = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_TYPE_2G);
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comp_value = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_VALUE_2G);
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if (!comp_type)
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comp_value = -comp_value;
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}
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} else {
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comp_en = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_ENABLE_5G);
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if (comp_en) {
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comp_type = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_TYPE_5G);
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comp_value = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_DELTA_VALUE_5G);
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if (!comp_type)
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comp_value = -comp_value;
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}
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}
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return comp_value;
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}
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static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
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int is_rate_b,
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enum ieee80211_band band,
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int power_level,
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u8 txpower)
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{
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u32 reg;
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u16 eeprom;
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u8 criterion;
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u8 eirp_txpower;
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u8 eirp_txpower_criterion;
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u8 reg_limit;
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int bw_comp = 0;
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if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
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return txpower;
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if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
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bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
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if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
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/*
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* Check if eirp txpower exceed txpower_limit.
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* We use OFDM 6M as criterion and its eirp txpower
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* is stored at EEPROM_EIRP_MAX_TX_POWER.
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* .11b data rate need add additional 4dbm
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* when calculating eirp txpower.
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*/
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®);
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criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
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rt2x00_eeprom_read(rt2x00dev,
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EEPROM_EIRP_MAX_TX_POWER, &eeprom);
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if (band == IEEE80211_BAND_2GHZ)
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eirp_txpower_criterion = rt2x00_get_field16(eeprom,
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EEPROM_EIRP_MAX_TX_POWER_2GHZ);
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else
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eirp_txpower_criterion = rt2x00_get_field16(eeprom,
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EEPROM_EIRP_MAX_TX_POWER_5GHZ);
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eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
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(is_rate_b ? 4 : 0) + bw_comp;
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reg_limit = (eirp_txpower > power_level) ?
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(eirp_txpower - power_level) : 0;
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} else
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reg_limit = 0;
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return txpower + bw_comp - reg_limit;
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}
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static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
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const int max_txpower)
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struct ieee80211_conf *conf)
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{
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u8 txpower;
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u8 max_value = (u8)max_txpower;
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u16 eeprom;
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int i;
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int i, is_rate_b;
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u32 reg;
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u8 r1;
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u32 offset;
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enum ieee80211_band band = conf->channel->band;
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int power_level = conf->power_level;
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/*
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* set to normal tx power mode: +/- 0dBm
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* set to normal bbp tx power control mode: +/- 0dBm
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*/
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rt2800_bbp_read(rt2x00dev, 1, &r1);
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rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
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rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
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rt2800_bbp_write(rt2x00dev, 1, r1);
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/*
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* The eeprom contains the tx power values for each rate. These
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* values map to 100% tx power. Each 16bit word contains four tx
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* power values and the order is the same as used in the TX_PWR_CFG
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* registers.
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*/
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offset = TX_PWR_CFG_0;
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for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
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@ -1721,73 +1807,99 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
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rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
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&eeprom);
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/* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
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is_rate_b = i ? 0 : 1;
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/*
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* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
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* TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE0);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE0,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
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/* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
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/*
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* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
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* TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE1);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE1,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
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/* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
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/*
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* TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
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* TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE2);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE2,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
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/* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
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/*
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* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
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* TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE3);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE3,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
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/* read the next four txpower values */
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rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
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&eeprom);
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/* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
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is_rate_b = 0;
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/*
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* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
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* TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE0);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE4,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
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/* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
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/*
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* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
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* TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE1);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE5,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
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/* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
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/*
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* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
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* TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE2);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE6,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
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/* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
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/*
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* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
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* TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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* TX_PWR_CFG_4: unknown
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*/
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE3);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE7,
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min(txpower, max_value));
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txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
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power_level, txpower);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
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rt2800_register_write(rt2x00dev, offset, reg);
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@ -1846,11 +1958,13 @@ void rt2800_config(struct rt2x00_dev *rt2x00dev,
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/* Always recalculate LNA gain before changing configuration */
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rt2800_config_lna_gain(rt2x00dev, libconf);
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if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
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if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
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rt2800_config_channel(rt2x00dev, libconf->conf,
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&libconf->rf, &libconf->channel);
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rt2800_config_txpower(rt2x00dev, libconf->conf);
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}
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if (flags & IEEE80211_CONF_CHANGE_POWER)
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rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
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rt2800_config_txpower(rt2x00dev, libconf->conf);
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if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
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rt2800_config_retry_limit(rt2x00dev, libconf);
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if (flags & IEEE80211_CONF_CHANGE_PS)
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@ -3040,13 +3154,6 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
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default_lna_gain);
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rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
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rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
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if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
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rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
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if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
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rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
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rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
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@ -3162,6 +3269,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
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rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
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#endif /* CONFIG_RT2X00_LIB_LEDS */
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/*
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* Check if support EIRP tx power limit feature.
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*/
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rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
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|
||||
if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
|
||||
EIRP_MAX_TX_POWER_LIMIT)
|
||||
__set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
|
||||
@ -3314,7 +3430,6 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
||||
char *default_power1;
|
||||
char *default_power2;
|
||||
unsigned int i;
|
||||
unsigned short max_power;
|
||||
u16 eeprom;
|
||||
|
||||
/*
|
||||
@ -3439,26 +3554,21 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
||||
|
||||
spec->channels_info = info;
|
||||
|
||||
rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
|
||||
max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
|
||||
default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
|
||||
default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
|
||||
|
||||
for (i = 0; i < 14; i++) {
|
||||
info[i].max_power = max_power;
|
||||
info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
|
||||
info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
|
||||
info[i].default_power1 = default_power1[i];
|
||||
info[i].default_power2 = default_power2[i];
|
||||
}
|
||||
|
||||
if (spec->num_channels > 14) {
|
||||
max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
|
||||
default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
|
||||
default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
|
||||
|
||||
for (i = 14; i < spec->num_channels; i++) {
|
||||
info[i].max_power = max_power;
|
||||
info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
|
||||
info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
|
||||
info[i].default_power1 = default_power1[i];
|
||||
info[i].default_power2 = default_power2[i];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -667,6 +667,7 @@ enum rt2x00_flags {
|
||||
*/
|
||||
CONFIG_SUPPORT_HW_BUTTON,
|
||||
CONFIG_SUPPORT_HW_CRYPTO,
|
||||
CONFIG_SUPPORT_POWER_LIMIT,
|
||||
DRIVER_SUPPORT_CONTROL_FILTERS,
|
||||
DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL,
|
||||
DRIVER_SUPPORT_PRE_TBTT_INTERRUPT,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user