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x86, mce: unify smp_thermal_interrupt, prepare
Let them in same shape. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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5335612a57
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e8ce2c5ee8
arch/x86
@ -110,6 +110,7 @@ extern int mce_disabled;
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extern int mce_p5_enabled;
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#ifdef CONFIG_X86_OLD_MCE
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extern int nr_mce_banks;
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void amd_mcheck_init(struct cpuinfo_x86 *c);
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void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
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void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
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@ -128,15 +129,6 @@ static inline void enable_p5_mce(void) {}
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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#ifdef CONFIG_X86_OLD_MCE
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extern int nr_mce_banks;
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extern void intel_set_thermal_handler(void);
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#else
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static inline void intel_set_thermal_handler(void) { }
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#endif
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, mce_dev);
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@ -175,8 +167,6 @@ int mce_available(struct cpuinfo_x86 *c);
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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void mce_log_therm_throt_event(__u64 status);
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extern atomic_t mce_entry;
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void do_machine_check(struct pt_regs *, long);
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@ -205,5 +195,18 @@ void mcheck_init(struct cpuinfo_x86 *c);
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extern void (*mce_threshold_vector)(void);
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/*
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* Thermal handler
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*/
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void intel_set_thermal_handler(void);
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void intel_init_thermal(struct cpuinfo_x86 *c);
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#ifdef CONFIG_X86_NEW_MCE
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void mce_log_therm_throt_event(__u64 status);
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#else
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static inline void mce_log_therm_throt_event(__u64 status) {}
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_MCE_H */
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@ -16,6 +16,14 @@
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#include <asm/idle.h>
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#include <asm/therm_throt.h>
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static void unexpected_thermal_interrupt(void)
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{
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printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
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smp_processor_id());
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* P4/Xeon Thermal transition interrupt handler: */
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static void intel_thermal_interrupt(void)
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{
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__u64 msr_val;
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@ -25,14 +33,22 @@ static void intel_thermal_interrupt(void)
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mce_log_therm_throt_event(msr_val);
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}
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/* Thermal interrupt handler for this CPU setup: */
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static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
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asmlinkage void smp_thermal_interrupt(void)
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{
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ack_APIC_irq();
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exit_idle();
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irq_enter();
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intel_thermal_interrupt();
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inc_irq_stat(irq_thermal_count);
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intel_thermal_interrupt();
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irq_exit();
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ack_APIC_irq();
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}
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void intel_set_thermal_handler(void)
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{
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vendor_thermal_interrupt = intel_thermal_interrupt;
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}
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/*
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@ -12,6 +12,7 @@
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/apic.h>
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#include <asm/idle.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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@ -47,10 +48,9 @@ static void intel_thermal_interrupt(void)
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{
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__u64 msr_val;
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ack_APIC_irq();
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rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
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therm_throt_process(msr_val & THERM_STATUS_PROCHOT);
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if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
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mce_log_therm_throt_event(msr_val);
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}
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/* Thermal interrupt handler for this CPU setup: */
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@ -58,10 +58,12 @@ static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
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void smp_thermal_interrupt(struct pt_regs *regs)
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{
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exit_idle();
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irq_enter();
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vendor_thermal_interrupt();
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inc_irq_stat(irq_thermal_count);
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vendor_thermal_interrupt();
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irq_exit();
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ack_APIC_irq();
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}
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void intel_set_thermal_handler(void)
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