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net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
This commit adds the definition of the PPv2.2 HW descriptors, adjusts the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts the accessors to work on both PPv2.1 and PPv2.2. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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@ -767,18 +767,42 @@ struct mvpp21_rx_desc {
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u32 reserved8;
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u32 reserved8;
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};
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};
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/* HW TX descriptor for PPv2.2 */
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struct mvpp22_tx_desc {
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u32 command;
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u8 packet_offset;
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u8 phys_txq;
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u16 data_size;
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u64 reserved1;
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u64 buf_dma_addr_ptp;
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u64 buf_cookie_misc;
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};
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/* HW RX descriptor for PPv2.2 */
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struct mvpp22_rx_desc {
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u32 status;
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u16 reserved1;
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u16 data_size;
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u32 reserved2;
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u32 reserved3;
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u64 buf_dma_addr_key_hash;
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u64 buf_cookie_misc;
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};
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/* Opaque type used by the driver to manipulate the HW TX and RX
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/* Opaque type used by the driver to manipulate the HW TX and RX
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* descriptors
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* descriptors
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*/
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*/
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struct mvpp2_tx_desc {
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struct mvpp2_tx_desc {
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union {
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union {
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struct mvpp21_tx_desc pp21;
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struct mvpp21_tx_desc pp21;
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struct mvpp22_tx_desc pp22;
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};
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};
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};
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};
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struct mvpp2_rx_desc {
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struct mvpp2_rx_desc {
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union {
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union {
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struct mvpp21_rx_desc pp21;
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struct mvpp21_rx_desc pp21;
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struct mvpp22_rx_desc pp22;
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};
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};
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};
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};
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@ -969,78 +993,118 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
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static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
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static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc)
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struct mvpp2_tx_desc *tx_desc)
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{
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{
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return tx_desc->pp21.buf_dma_addr;
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if (port->priv->hw_version == MVPP21)
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return tx_desc->pp21.buf_dma_addr;
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else
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return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0);
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}
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}
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static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
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static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct mvpp2_tx_desc *tx_desc,
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dma_addr_t dma_addr)
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dma_addr_t dma_addr)
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{
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{
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tx_desc->pp21.buf_dma_addr = dma_addr;
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if (port->priv->hw_version == MVPP21) {
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tx_desc->pp21.buf_dma_addr = dma_addr;
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} else {
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u64 val = (u64)dma_addr;
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tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
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tx_desc->pp22.buf_dma_addr_ptp |= val;
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}
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}
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}
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static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
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static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc)
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struct mvpp2_tx_desc *tx_desc)
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{
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{
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return tx_desc->pp21.data_size;
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if (port->priv->hw_version == MVPP21)
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return tx_desc->pp21.data_size;
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else
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return tx_desc->pp22.data_size;
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}
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}
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static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
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static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct mvpp2_tx_desc *tx_desc,
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size_t size)
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size_t size)
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{
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{
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tx_desc->pp21.data_size = size;
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if (port->priv->hw_version == MVPP21)
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tx_desc->pp21.data_size = size;
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else
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tx_desc->pp22.data_size = size;
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}
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}
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static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
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static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct mvpp2_tx_desc *tx_desc,
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unsigned int txq)
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unsigned int txq)
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{
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{
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tx_desc->pp21.phys_txq = txq;
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if (port->priv->hw_version == MVPP21)
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tx_desc->pp21.phys_txq = txq;
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else
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tx_desc->pp22.phys_txq = txq;
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}
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}
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static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
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static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct mvpp2_tx_desc *tx_desc,
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unsigned int command)
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unsigned int command)
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{
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{
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tx_desc->pp21.command = command;
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if (port->priv->hw_version == MVPP21)
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tx_desc->pp21.command = command;
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else
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tx_desc->pp22.command = command;
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}
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}
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static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
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static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct mvpp2_tx_desc *tx_desc,
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unsigned int offset)
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unsigned int offset)
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{
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{
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tx_desc->pp21.packet_offset = offset;
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if (port->priv->hw_version == MVPP21)
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tx_desc->pp21.packet_offset = offset;
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else
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tx_desc->pp22.packet_offset = offset;
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}
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}
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static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
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static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc)
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struct mvpp2_tx_desc *tx_desc)
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{
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{
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return tx_desc->pp21.packet_offset;
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if (port->priv->hw_version == MVPP21)
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return tx_desc->pp21.packet_offset;
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else
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return tx_desc->pp22.packet_offset;
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}
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}
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static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
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static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc)
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struct mvpp2_rx_desc *rx_desc)
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{
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{
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return rx_desc->pp21.buf_dma_addr;
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if (port->priv->hw_version == MVPP21)
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return rx_desc->pp21.buf_dma_addr;
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else
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return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
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}
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}
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static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
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static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc)
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struct mvpp2_rx_desc *rx_desc)
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{
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{
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return rx_desc->pp21.buf_cookie;
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if (port->priv->hw_version == MVPP21)
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return rx_desc->pp21.buf_cookie;
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else
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return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
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}
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}
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static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
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static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc)
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struct mvpp2_rx_desc *rx_desc)
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{
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{
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return rx_desc->pp21.data_size;
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if (port->priv->hw_version == MVPP21)
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return rx_desc->pp21.data_size;
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else
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return rx_desc->pp22.data_size;
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}
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}
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static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
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static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc)
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struct mvpp2_rx_desc *rx_desc)
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{
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{
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return rx_desc->pp21.status;
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if (port->priv->hw_version == MVPP21)
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return rx_desc->pp21.status;
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else
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return rx_desc->pp22.status;
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}
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}
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static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
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static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
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