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drm/i915: Account for scale factor when calculating initial phase
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was mostly looking at
heavily upscaled content where the minor difference between -0.5
and the proper initial phase was not readily apparent.
And let's toss in a comment that tries to explain the formula
a little bit.
v2: The initial phase upper limit is 1.5, not 24.0!
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: 0a59952b24
("drm/i915: Configure SKL+ scaler initial phase correctly")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181029181820.21956-1-ville.syrjala@linux.intel.com
Tested-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Tested-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
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ca0026790e
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@ -4777,8 +4777,31 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
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* chroma samples for both of the luma samples, and thus we don't
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* actually get the expected MPEG2 chroma siting convention :(
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* The same behaviour is observed on pre-SKL platforms as well.
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*
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* Theory behind the formula (note that we ignore sub-pixel
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* source coordinates):
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* s = source sample position
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* d = destination sample position
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*
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* Downscaling 4:1:
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* -0.5
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* | 0.0
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* | | 1.5 (initial phase)
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* | | |
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* v v v
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* | s | s | s | s |
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* | d |
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*
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* Upscaling 1:4:
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* -0.5
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* | -0.375 (initial phase)
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* | | 0.0
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* | | |
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* v v v
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* | s |
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* | d | d | d | d |
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*/
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u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
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{
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int phase = -0x8000;
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u16 trip = 0;
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@ -4786,6 +4809,15 @@ u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
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if (chroma_cosited)
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phase += (sub - 1) * 0x8000 / sub;
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phase += scale / (2 * sub);
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/*
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* Hardware initial phase limited to [-0.5:1.5].
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* Since the max hardware scale factor is 3.0, we
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* should never actually excdeed 1.0 here.
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*/
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WARN_ON(phase < -0x8000 || phase > 0x18000);
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if (phase < 0)
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phase = 0x10000 + phase;
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else
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@ -4994,13 +5026,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
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if (crtc_state->pch_pfit.enabled) {
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u16 uv_rgb_hphase, uv_rgb_vphase;
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int pfit_w, pfit_h, hscale, vscale;
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int id;
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if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
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return;
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uv_rgb_hphase = skl_scaler_calc_phase(1, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, false);
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pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
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pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
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hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
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vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
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uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
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id = scaler_state->scaler_id;
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I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
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@ -1720,7 +1720,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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u16 skl_scaler_calc_phase(int sub, bool chroma_center);
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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int skl_max_scale(const struct intel_crtc_state *crtc_state,
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u32 pixel_format);
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@ -326,23 +326,31 @@ skl_program_scaler(struct intel_plane *plane,
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uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
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u16 y_hphase, uv_rgb_hphase;
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u16 y_vphase, uv_rgb_vphase;
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int hscale, vscale;
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hscale = drm_rect_calc_hscale(&plane_state->base.src,
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&plane_state->base.dst,
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0, INT_MAX);
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vscale = drm_rect_calc_vscale(&plane_state->base.src,
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&plane_state->base.dst,
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0, INT_MAX);
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/* TODO: handle sub-pixel coordinates */
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if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
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!icl_is_hdr_plane(plane)) {
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y_hphase = skl_scaler_calc_phase(1, false);
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y_vphase = skl_scaler_calc_phase(1, false);
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y_hphase = skl_scaler_calc_phase(1, hscale, false);
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y_vphase = skl_scaler_calc_phase(1, vscale, false);
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/* MPEG2 chroma siting convention */
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uv_rgb_hphase = skl_scaler_calc_phase(2, true);
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uv_rgb_vphase = skl_scaler_calc_phase(2, false);
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uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
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uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
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} else {
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/* not used */
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y_hphase = 0;
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y_vphase = 0;
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uv_rgb_hphase = skl_scaler_calc_phase(1, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, false);
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uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
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}
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I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
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