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sched/rt, ARM: Use CONFIG_PREEMPTION
CONFIG_PREEMPTION is selected by CONFIG_PREEMPT and by CONFIG_PREEMPT_RT. Both PREEMPT and PREEMPT_RT require the same functionality which today depends on CONFIG_PREEMPT. Switch the entry code, cache over to use CONFIG_PREEMPTION and add output in show_stack() for PREEMPT_RT. [bigeasy: +traps.c] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20191015191821.11479-2-bigeasy@linutronix.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -10,7 +10,7 @@
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* to ensure that the maintenance completes in case we migrate to another
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* CPU.
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*/
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#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
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#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
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#define __complete_pending_tlbi() dsb(ish)
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#else
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#define __complete_pending_tlbi()
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@ -211,7 +211,7 @@ __irq_svc:
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svc_entry
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irq_handler
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
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ldr r0, [tsk, #TI_FLAGS] @ get flags
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teq r8, #0 @ if preempt count != 0
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@ -226,7 +226,7 @@ ENDPROC(__irq_svc)
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.ltorg
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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svc_preempt:
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mov r8, lr
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1: bl preempt_schedule_irq @ irq en/disable is done inside
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@ -248,6 +248,8 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
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#ifdef CONFIG_PREEMPT
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#define S_PREEMPT " PREEMPT"
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#elif defined(CONFIG_PREEMPT_RT)
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#define S_PREEMPT " PREEMPT_RT"
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#else
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#define S_PREEMPT ""
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#endif
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@ -135,13 +135,13 @@ flush_levels:
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
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#endif
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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restore_irqs_notrace r9
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#endif
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and r2, r1, #7 @ extract the length of the cache lines
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@ -183,13 +183,13 @@ flush_levels:
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
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#endif
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write_csselr r10, r1 @ set current cache level
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isb @ isb to sych the new cssr&csidr
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read_ccsidr r1 @ read the new csidr
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#ifdef CONFIG_PREEMPT
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#ifdef CONFIG_PREEMPTION
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restore_irqs_notrace r9
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#endif
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and r2, r1, #7 @ extract the length of the cache lines
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