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ARM: LPC32XX: Serial support code
Serial port setup support code Signed-off-by: Kevin Wells <wellsk40@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Kevin Wells
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190
arch/arm/mach-lpc32xx/serial.c
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190
arch/arm/mach-lpc32xx/serial.c
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/*
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* arch/arm/mach-lpc32xx/serial.c
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "common.h"
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#define LPC32XX_SUART_FIFO_SIZE 64
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/* Standard 8250/16550 compatible serial ports */
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static struct plat_serial8250_port serial_std_platform_data[] = {
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#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
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{
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.membase = io_p2v(LPC32XX_UART5_BASE),
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.mapbase = LPC32XX_UART5_BASE,
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.irq = IRQ_LPC32XX_UART_IIR5,
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.uartclk = LPC32XX_MAIN_OSC_FREQ,
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.regshift = 2,
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.iotype = UPIO_MEM32,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
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UPF_SKIP_TEST,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
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{
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.membase = io_p2v(LPC32XX_UART3_BASE),
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.mapbase = LPC32XX_UART3_BASE,
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.irq = IRQ_LPC32XX_UART_IIR3,
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.uartclk = LPC32XX_MAIN_OSC_FREQ,
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.regshift = 2,
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.iotype = UPIO_MEM32,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
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UPF_SKIP_TEST,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
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{
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.membase = io_p2v(LPC32XX_UART4_BASE),
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.mapbase = LPC32XX_UART4_BASE,
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.irq = IRQ_LPC32XX_UART_IIR4,
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.uartclk = LPC32XX_MAIN_OSC_FREQ,
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.regshift = 2,
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.iotype = UPIO_MEM32,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
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UPF_SKIP_TEST,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
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{
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.membase = io_p2v(LPC32XX_UART6_BASE),
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.mapbase = LPC32XX_UART6_BASE,
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.irq = IRQ_LPC32XX_UART_IIR6,
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.uartclk = LPC32XX_MAIN_OSC_FREQ,
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.regshift = 2,
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.iotype = UPIO_MEM32,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
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UPF_SKIP_TEST,
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},
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#endif
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{ },
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};
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struct uartinit {
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char *uart_ck_name;
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u32 ck_mode_mask;
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void __iomem *pdiv_clk_reg;
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};
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static struct uartinit uartinit_data[] __initdata = {
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#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
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{
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.uart_ck_name = "uart5_ck",
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
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{
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.uart_ck_name = "uart3_ck",
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
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{
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.uart_ck_name = "uart4_ck",
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
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{
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.uart_ck_name = "uart6_ck",
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
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},
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#endif
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};
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static struct platform_device serial_std_platform_device = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = serial_std_platform_data,
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},
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};
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static struct platform_device *lpc32xx_serial_devs[] __initdata = {
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&serial_std_platform_device,
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};
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void __init lpc32xx_serial_init(void)
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{
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u32 tmp, clkmodes = 0;
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struct clk *clk;
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unsigned int puart;
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int i, j;
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/* UART clocks are off, let clock driver manage them */
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__raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
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for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
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clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
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if (!IS_ERR(clk)) {
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clk_enable(clk);
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serial_std_platform_data[i].uartclk =
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clk_get_rate(clk);
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}
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/* Fall back on main osc rate if clock rate return fails */
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if (serial_std_platform_data[i].uartclk == 0)
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serial_std_platform_data[i].uartclk =
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LPC32XX_MAIN_OSC_FREQ;
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/* Setup UART clock modes for all UARTs, disable autoclock */
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clkmodes |= uartinit_data[i].ck_mode_mask;
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/* pre-UART clock divider set to 1 */
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__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
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}
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/* This needs to be done after all UART clocks are setup */
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__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
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for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
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/* Force a flush of the RX FIFOs to work around a HW bug */
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puart = serial_std_platform_data[i].mapbase;
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__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
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__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
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j = LPC32XX_SUART_FIFO_SIZE;
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while (j--)
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tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
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__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
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}
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/* Disable UART5->USB transparent mode or USB won't work */
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tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
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tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
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__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
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platform_add_devices(lpc32xx_serial_devs,
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ARRAY_SIZE(lpc32xx_serial_devs));
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}
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