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clocksource/drivers/sp804: Prepare for support non-standard register offset
Add two local variables: timer1_base and timer2_base in sp804_of_init(), to avoid repeatedly calculate the base address of timer2, and make it easier to recognize timer1. Hope to make the next patch looks more clear. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200918132237.3552-6-thunder.leizhen@huawei.com
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@ -188,6 +188,8 @@ static int __init sp804_of_init(struct device_node *np)
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{
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static bool initialized = false;
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void __iomem *base;
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void __iomem *timer1_base;
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void __iomem *timer2_base;
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int irq, ret = -EINVAL;
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u32 irq_num = 0;
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struct clk *clk1, *clk2;
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@ -197,9 +199,12 @@ static int __init sp804_of_init(struct device_node *np)
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if (!base)
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return -ENXIO;
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timer1_base = base;
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timer2_base = base + TIMER_2_BASE;
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/* Ensure timers are disabled */
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writel(0, base + TIMER_CTRL);
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writel(0, base + TIMER_2_BASE + TIMER_CTRL);
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writel(0, timer1_base + TIMER_CTRL);
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writel(0, timer2_base + TIMER_CTRL);
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if (initialized || !of_device_is_available(np)) {
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ret = -EINVAL;
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@ -228,21 +233,21 @@ static int __init sp804_of_init(struct device_node *np)
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of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
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if (irq_num == 2) {
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ret = sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
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ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
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if (ret)
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goto err;
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ret = sp804_clocksource_and_sched_clock_init(base,
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ret = sp804_clocksource_and_sched_clock_init(timer1_base,
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name, clk1, 1);
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if (ret)
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goto err;
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} else {
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ret = sp804_clockevents_init(base, irq, clk1, name);
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ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
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if (ret)
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goto err;
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ret = sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
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ret = sp804_clocksource_and_sched_clock_init(timer2_base,
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name, clk2, 1);
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if (ret)
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goto err;
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