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drm/sun4i: Fix dclk_set_phase

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Phase value is not shifted before writing.

Shift left of 28 bits to fit right bits

Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1519836413-35023-1-git-send-email-giulio.benetti@micronovasrl.com
This commit is contained in:
Giulio Benetti 2018-02-28 17:46:53 +01:00 committed by Maxime Ripard
parent 9a191b1149
commit e64b6afa98
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1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/sun4i/sun4i_dotclock.c
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@ -132,10 +132,13 @@ static int sun4i_dclk_get_phase(struct clk_hw *hw)
static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
{
struct sun4i_dclk *dclk = hw_to_dclk(hw);
u32 val = degrees / 120;
val <<= 28;
regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
GENMASK(29, 28),
degrees / 120);
val);
return 0;
}