mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
drm/nv44/vm: fix and enable use of "real" pciegart
Something seems to be missing in regards to flushing specific ranges of the TLB. For the moment, flushing the entire thing seems to make it work alright. Should give 39-bit DMA addressing on the relevant chipsets. v2: allocate contig 16KiB for dummy pages, reported by mwk on irc Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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8a57d279d6
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@ -218,7 +218,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -238,7 +238,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -258,7 +258,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -278,7 +278,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -298,7 +298,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -318,7 +318,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -338,7 +338,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -358,7 +358,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
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@ -132,10 +132,9 @@ nv04_vmmgr_dtor(struct nouveau_object *object)
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nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
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nouveau_vm_ref(NULL, &priv->vm, NULL);
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}
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if (priv->page) {
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pci_unmap_page(nv_device(priv)->pdev, priv->null,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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__free_page(priv->page);
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if (priv->nullp) {
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pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
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priv->nullp, priv->null);
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}
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nouveau_vmmgr_destroy(&priv->base);
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}
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@ -6,8 +6,8 @@
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struct nv04_vmmgr_priv {
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struct nouveau_vmmgr base;
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struct nouveau_vm *vm;
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struct page *page;
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dma_addr_t null;
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void *nullp;
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};
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static inline struct nv04_vmmgr_priv *
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@ -23,6 +23,7 @@
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*/
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#include <core/gpuobj.h>
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#include <core/option.h>
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#include <subdev/timer.h>
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#include <subdev/vm.h>
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@ -36,16 +37,6 @@
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* VM map/unmap callbacks
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******************************************************************************/
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static void
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nv44_vm_flush_priv(struct nv04_vmmgr_priv *priv, u32 base, u32 size)
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{
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nv_wr32(priv, 0x100814, (size - 1) << 12);
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nv_wr32(priv, 0x100808, base | 0x20);
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if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
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nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
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nv_wr32(priv, 0x100808, 0x00000000);
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}
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static void
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nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
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dma_addr_t *list, u32 pte, u32 cnt)
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@ -57,6 +48,7 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
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tmp[1] = nv_ro32(pgt, base + 0x4);
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tmp[2] = nv_ro32(pgt, base + 0x8);
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tmp[3] = nv_ro32(pgt, base + 0xc);
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while (cnt--) {
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u32 addr = list ? (*list++ >> 12) : (null >> 12);
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switch (pte++ & 0x3) {
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@ -96,8 +88,6 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
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{
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struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
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u32 base = pte << 12;
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u32 size = cnt;
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u32 tmp[4];
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int i;
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@ -122,15 +112,12 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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if (cnt)
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nv44_vm_fill(pgt, priv->null, list, pte, cnt);
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nv44_vm_flush_priv(priv, base, size);
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}
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static void
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nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
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{
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struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
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u32 base = pte << 12;
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u32 size = cnt;
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if (pte & 3) {
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u32 max = 4 - (pte & 3);
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@ -150,12 +137,17 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
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if (cnt)
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nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);
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nv44_vm_flush_priv(priv, base, size);
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}
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static void
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nv44_vm_flush(struct nouveau_vm *vm)
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{
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struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
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nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
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nv_wr32(priv, 0x100808, 0x00000020);
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if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
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nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
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nv_wr32(priv, 0x100808, 0x00000000);
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}
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/*******************************************************************************
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@ -171,6 +163,11 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nv04_vmmgr_priv *priv;
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int ret;
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if (!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
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return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
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data, size, pobject);
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}
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ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
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"pciegart", &priv);
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*pobject = nv_object(priv);
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@ -187,19 +184,11 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->base.unmap = nv44_vm_unmap;
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priv->base.flush = nv44_vm_flush;
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priv->page = alloc_page(GFP_DMA32 | GFP_KERNEL);
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if (priv->page) {
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priv->null = pci_map_page(device->pdev, priv->page, 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(device->pdev, priv->null)) {
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__free_page(priv->page);
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priv->page = NULL;
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priv->null = 0;
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priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null);
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if (!priv->nullp) {
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nv_error(priv, "unable to allocate dummy pages\n");
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return -ENOMEM;
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}
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}
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if (!priv->page)
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nv_warn(priv, "unable to allocate dummy page\n");
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ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
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&priv->vm);
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