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Staging: et131x: clean up MMC_SRAM_
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -2264,7 +2264,7 @@ typedef struct _MAC_STAT_t { /* Location: */
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/* START OF MMC REGISTER ADDRESS MAP */
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/*
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* structure for Main Memory Controller Control reg in mmc address map.
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* Main Memory Controller Control reg in mmc address map.
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* located at address 0x7000
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*/
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@ -2277,31 +2277,13 @@ typedef struct _MAC_STAT_t { /* Location: */
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#define ET_MMC_FORCE_CE 64
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/*
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* structure for Main Memory Controller Host Memory Access Address reg in mmc
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* address map. Located at address 0x7004
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* Main Memory Controller Host Memory Access Address reg in mmc
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* address map. Located at address 0x7004. Top 16 bits hold the address bits
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*/
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typedef union _MMC_SRAM_ACCESS_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 byte_enable:16; /* bits 16-31 */
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u32 reserved2:2; /* bits 14-15 */
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u32 req_addr:10; /* bits 4-13 */
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u32 reserved1:1; /* bit 3 */
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u32 is_ctrl_word:1; /* bit 2 */
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u32 wr_access:1; /* bit 1 */
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u32 req_access:1; /* bit 0 */
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#else
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u32 req_access:1; /* bit 0 */
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u32 wr_access:1; /* bit 1 */
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u32 is_ctrl_word:1; /* bit 2 */
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u32 reserved1:1; /* bit 3 */
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u32 req_addr:10; /* bits 4-13 */
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u32 reserved2:2; /* bits 14-15 */
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u32 byte_enable:16; /* bits 16-31 */
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#endif
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} bits;
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} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
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#define ET_SRAM_REQ_ACCESS 1
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#define ET_SRAM_WR_ACCESS 2
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#define ET_SRAM_IS_CTRL 4
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/*
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* structure for Main Memory Controller Host Memory Access Data reg in mmc
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@ -2314,7 +2296,7 @@ typedef union _MMC_SRAM_ACCESS_t {
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*/
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typedef struct _MMC_t { /* Location: */
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u32 mmc_ctrl; /* 0x7000 */
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MMC_SRAM_ACCESS_t sram_access; /* 0x7004 */
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u32 sram_access; /* 0x7004 */
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u32 sram_word1; /* 0x7008 */
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u32 sram_word2; /* 0x700C */
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u32 sram_word3; /* 0x7010 */
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@ -115,18 +115,16 @@ void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
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if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
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for (TxQueueAddr = 0x200; TxQueueAddr < 0x3ff; TxQueueAddr++) {
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MMC_SRAM_ACCESS_t sram_access;
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sram_access.value = readl(&mmc->sram_access.value);
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sram_access.bits.req_addr = TxQueueAddr;
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sram_access.bits.req_access = 1;
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writel(sram_access.value, &mmc->sram_access.value);
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u32 sram_access = readl(&mmc->sram_access);
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sram_access &= 0xFFFF;
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sram_access |= (TxQueueAddr << 16) | ET_SRAM_REQ_ACCESS;
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writel(sram_access, &mmc->sram_access);
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DBG_PRINT("Addr 0x%x, Access 0x%08x\t"
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"Value 1 0x%08x, Value 2 0x%08x, "
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"Value 3 0x%08x, Value 4 0x%08x, \n",
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TxQueueAddr,
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readl(&mmc->sram_access.value),
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readl(&mmc->sram_access),
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readl(&mmc->sram_word1),
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readl(&mmc->sram_word2),
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readl(&mmc->sram_word3),
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