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KVM: PPC: bookehv64: Add support for interrupt handling
Add interrupt handling support for 64-bit bookehv hosts. Unify 32 and 64 bit implementations using a common stack layout and a common execution flow starting from kvm_handler_common macro. Update documentation for 64-bit input register values. This patch only address the bolted TLB miss exception handlers version. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Mihai Caraman
Alexander Graf
parent
ff59474684
commit
e51f8f32d6
@ -17,6 +17,7 @@
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* there are no exceptions for which we fall through directly to
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* the normal host handler.
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*
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* 32-bit host
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* Expected inputs (normal exceptions):
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* SCRATCH0 = saved r10
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* r10 = thread struct
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@ -33,6 +34,30 @@
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* *(r8 + GPR9) = saved r9
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* *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
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* *(r8 + GPR11) = saved r11
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*
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* 64-bit host
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* Expected inputs (GEN/GDBELL/DBG/MC exception types):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_R11) = saved r11
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* SPRN_SPRG_##type##_SCRATCH = saved r13
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*
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* Expected inputs (CRIT exception type):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_R11) = saved r11
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* *(r13 + PACA_EX##type + EX_R13) = saved r13
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*
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* Expected inputs (TLB exception type):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11
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* SPRN_SPRG_GEN_SCRATCH = saved r13
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*
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* Only the bolted version of TLB miss exception handlers is supported now.
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*/
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.macro DO_KVM intno srr1
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#ifdef CONFIG_KVM_BOOKE_HV
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@ -16,6 +16,7 @@
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*
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* Author: Varun Sethi <varun.sethi@freescale.com>
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* Author: Scott Wood <scotwood@freescale.com>
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* Author: Mihai Caraman <mihai.caraman@freescale.com>
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*
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* This file is derived from arch/powerpc/kvm/booke_interrupts.S
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*/
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@ -30,28 +31,33 @@
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#include <asm/bitsperlong.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_64BIT
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#include <asm/exception-64e.h>
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#else
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#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
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#endif
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#define LONGBYTES (BITS_PER_LONG / 8)
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#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
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/* The host stack layout: */
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#define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */
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#define HOST_CALLEE_LR (1 * LONGBYTES)
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#define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */
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#define HOST_R1 0 /* Implied by stwu. */
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#define HOST_CALLEE_LR PPC_LR_STKOFF
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#define HOST_RUN (HOST_CALLEE_LR + LONGBYTES)
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/*
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* r2 is special: it holds 'current', and it made nonvolatile in the
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* kernel with the -ffixed-r2 gcc option.
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*/
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#define HOST_R2 (3 * LONGBYTES)
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#define HOST_CR (4 * LONGBYTES)
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#define HOST_NV_GPRS (5 * LONGBYTES)
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#define HOST_R2 (HOST_RUN + LONGBYTES)
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#define HOST_CR (HOST_R2 + LONGBYTES)
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#define HOST_NV_GPRS (HOST_CR + LONGBYTES)
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#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
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#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
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#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
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#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
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#define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
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/* LR in caller stack frame. */
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#define HOST_STACK_LR (HOST_STACK_SIZE + PPC_LR_STKOFF)
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#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
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#define NEED_DEAR 0x00000002 /* save faulting DEAR */
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@ -198,6 +204,122 @@
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b kvmppc_resume_host
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.endm
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#ifdef CONFIG_64BIT
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/* Exception types */
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#define EX_GEN 1
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#define EX_GDBELL 2
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#define EX_DBG 3
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#define EX_MC 4
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#define EX_CRIT 5
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#define EX_TLB 6
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/*
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* For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
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*/
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.macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
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_GLOBAL(kvmppc_handler_\intno\()_\srr1)
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mr r11, r4
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/*
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* Get vcpu from Paca: paca->__current.thread->kvm_vcpu
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*/
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PPC_LL r4, PACACURRENT(r13)
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PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
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stw r10, VCPU_CR(r4)
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PPC_STL r11, VCPU_GPR(R4)(r4)
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PPC_STL r5, VCPU_GPR(R5)(r4)
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.if \type == EX_CRIT
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PPC_LL r5, (\paca_ex + EX_R13)(r13)
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.else
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mfspr r5, \scratch
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.endif
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PPC_STL r6, VCPU_GPR(R6)(r4)
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PPC_STL r8, VCPU_GPR(R8)(r4)
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PPC_STL r9, VCPU_GPR(R9)(r4)
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PPC_STL r5, VCPU_GPR(R13)(r4)
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PPC_LL r6, (\paca_ex + \ex_r10)(r13)
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PPC_LL r8, (\paca_ex + \ex_r11)(r13)
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PPC_STL r3, VCPU_GPR(R3)(r4)
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PPC_STL r7, VCPU_GPR(R7)(r4)
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PPC_STL r12, VCPU_GPR(R12)(r4)
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PPC_STL r6, VCPU_GPR(R10)(r4)
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PPC_STL r8, VCPU_GPR(R11)(r4)
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mfctr r5
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PPC_STL r5, VCPU_CTR(r4)
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mfspr r5, \srr0
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mfspr r6, \srr1
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kvm_handler_common \intno, \srr0, \flags
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.endm
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#define EX_PARAMS(type) \
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EX_##type, \
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SPRN_SPRG_##type##_SCRATCH, \
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PACA_EX##type, \
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EX_R10, \
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EX_R11
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#define EX_PARAMS_TLB \
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EX_TLB, \
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SPRN_SPRG_GEN_SCRATCH, \
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PACA_EXTLB, \
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EX_TLB_R10, \
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EX_TLB_R11
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kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
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SPRN_CSRR0, SPRN_CSRR1, 0
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kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
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SPRN_MCSRR0, SPRN_MCSRR1, 0
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kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
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kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, NEED_ESR
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kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
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kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1,NEED_ESR
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kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
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SPRN_CSRR0, SPRN_CSRR1, 0
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/*
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* Only bolted TLB miss exception handlers are supported for now
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*/
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kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
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SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
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kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
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SPRN_CSRR0, SPRN_CSRR1, 0
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kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, NEED_EMU
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kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
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SPRN_SRR0, SPRN_SRR1, 0
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kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
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SPRN_GSRR0, SPRN_GSRR1, 0
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kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
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SPRN_CSRR0, SPRN_CSRR1, 0
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kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
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SPRN_DSRR0, SPRN_DSRR1, 0
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kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
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SPRN_CSRR0, SPRN_CSRR1, 0
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#else
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/*
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* For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
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*/
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@ -292,7 +414,7 @@ kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
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SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
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kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
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SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
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#endif
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/* Registers:
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* SPRG_SCRATCH0: guest r10
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