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clk: stm32mp1: add Sub System clocks
The RCC handles three sub-system clocks: ck_mpuss, ck_axiss and ck_mcuss. This patch adds also some MUX system and several prescalers. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -116,6 +116,42 @@ static const char * const ref4_parents[] = {
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"ck_hsi", "ck_hse", "ck_csi"
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};
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static const char * const cpu_src[] = {
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"ck_hsi", "ck_hse", "pll1_p"
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};
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static const char * const axi_src[] = {
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"ck_hsi", "ck_hse", "pll2_p", "pll3_p"
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};
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static const char * const per_src[] = {
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"ck_hsi", "ck_csi", "ck_hse"
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};
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static const char * const mcu_src[] = {
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"ck_hsi", "ck_hse", "ck_csi", "pll3_p"
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};
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static const struct clk_div_table axi_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
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{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
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{ 0 },
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};
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static const struct clk_div_table mcu_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
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{ 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
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{ 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
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{ 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
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{ 0 },
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};
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static const struct clk_div_table apb_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
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{ 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
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{ 0 },
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};
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struct clock_config {
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u32 id;
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const char *name;
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@ -781,6 +817,21 @@ _clk_stm32_register_composite(struct device *dev,
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_STM32_DIV(_div_offset, _div_shift, _div_width,\
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_div_flags, _div_table, NULL)\
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#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _ops)\
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.mux = &(struct stm32_mux_cfg) {\
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&(struct mux_cfg) {\
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.reg_off = _offset,\
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.shift = _shift,\
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.width = _width,\
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.mux_flags = _mux_flags,\
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.table = NULL,\
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},\
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.ops = _ops,\
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}
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#define _MUX(_offset, _shift, _width, _mux_flags)\
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_STM32_MUX(_offset, _shift, _width, _mux_flags, NULL)\
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#define PARENT(_parent) ((const char *[]) { _parent})
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#define _NO_MUX .mux = NULL
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@ -882,6 +933,40 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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_GATE(RCC_PLL4CR, 6, 0),
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_NO_MUX,
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_DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
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/* MUX system clocks */
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MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
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RCC_CPERCKSELR, 0, 2, 0),
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MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
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CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
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COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
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CLK_OPS_PARENT_ENABLE,
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_NO_GATE,
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_MUX(RCC_ASSCKSELR, 0, 2, 0),
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_DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
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COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
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CLK_OPS_PARENT_ENABLE,
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_NO_GATE,
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_MUX(RCC_MSSCKSELR, 0, 2, 0),
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_DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
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DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
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3, CLK_DIVIDER_READ_ONLY, apb_div_table),
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DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
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3, CLK_DIVIDER_READ_ONLY, apb_div_table),
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DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
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3, CLK_DIVIDER_READ_ONLY, apb_div_table),
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DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
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3, CLK_DIVIDER_READ_ONLY, apb_div_table),
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DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
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3, CLK_DIVIDER_READ_ONLY, apb_div_table),
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};
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struct stm32_clock_match_data {
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