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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

Browse Source 
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Fix CONFIG_BOOT_RAW.
  [MIPS] Assume R4000/R4400 newer than 3.0 don't have the mfc0 count bug
  [MIPS] Fix IP32 breakage
  [MIPS] Alchemy: Fix use of __init code bug exposed by modpost warning
  [MIPS] Move inclusing of kernel/time/Kconfig menu to appropriate place
This commit is contained in:
Linus Torvalds 2008-01-07 13:31:03 -08:00
commit e4c6d3c6b1
9 changed files with 57 additions and 47 deletions
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4
arch/mips/Kconfig
View File

@ -992,8 +992,6 @@ config BOOT_ELF64
menu "CPU selection"
source "kernel/time/Kconfig"
choice
prompt "CPU type"
default CPU_R4X00
@ -1768,6 +1766,8 @@ config NR_CPUS
performance should round up your number of processors to the next
power of two.
source "kernel/time/Kconfig"
#
# Timer Interrupt Frequency Configuration
#

8
arch/mips/au1000/common/pci.c
View File

@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
* Alchemy/AMD Au1x00 pci support.
* Alchemy/AMD Au1x00 PCI support.
*
* Copyright 2001,2002,2003 MontaVista Software Inc.
* Copyright 2001-2003, 2007 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
@ -66,6 +66,8 @@ static unsigned long virt_io_addr;
static int __init au1x_pci_setup(void)
{
extern void au1x_pci_cfg_init(void);
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
@ -94,6 +96,8 @@ static int __init au1x_pci_setup(void)
set_io_port_base(virt_io_addr);
#endif
au1x_pci_cfg_init();
register_pci_controller(&au1x_controller);
return 0;
}

3
arch/mips/kernel/head.S
View File

@ -136,7 +136,8 @@ EXPORT(_stext)
* kernel load address. This is needed because this platform does
* not have a ELF loader yet.
*/
__INIT
FEXPORT(__kernel_entry)
j kernel_entry
#endif
__INIT_REFOK

4
arch/mips/kernel/time.c
View File

@ -147,9 +147,9 @@ static __init int cpu_has_mfc0_count_bug(void)
return 1;
/*
* I don't have erratas for newer R4400 so be paranoid.
* we assume newer revisions are ok
*/
return 1;
return 0;
}
return 0;

53
arch/mips/pci/ops-au1000.c
View File

@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
* Alchemy/AMD Au1x00 pci support.
* Alchemy/AMD Au1x00 PCI support.
*
* Copyright 2001,2002,2003 MontaVista Software Inc.
* Copyright 2001-2003, 2007 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
@ -69,10 +69,27 @@ void mod_wired_entry(int entry, unsigned long entrylo0,
write_c0_pagemask(old_pagemask);
}
struct vm_struct *pci_cfg_vm;
static struct vm_struct *pci_cfg_vm;
static int pci_cfg_wired_entry;
static int first_cfg = 1;
unsigned long last_entryLo0, last_entryLo1;
static unsigned long last_entryLo0, last_entryLo1;
/*
* We can't ioremap the entire pci config space because it's too large.
* Nor can we call ioremap dynamically because some device drivers use
* the PCI config routines from within interrupt handlers and that
* becomes a problem in get_vm_area(). We use one wired TLB to handle
* all config accesses for all busses.
*/
void __init au1x_pci_cfg_init(void)
{
/* Reserve a wired entry for PCI config accesses */
pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
if (!pci_cfg_vm)
panic(KERN_ERR "PCI unable to get vm area\n");
pci_cfg_wired_entry = read_c0_wired();
add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
last_entryLo0 = last_entryLo1 = 0xffffffff;
}
static int config_access(unsigned char access_type, struct pci_bus *bus,
unsigned int dev_fn, unsigned char where,
@ -97,27 +114,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
Au1500_PCI_STATCMD);
au_sync_udelay(1);
/*
* We can't ioremap the entire pci config space because it's
* too large. Nor can we call ioremap dynamically because some
* device drivers use the pci config routines from within
* interrupt handlers and that becomes a problem in get_vm_area().
* We use one wired tlb to handle all config accesses for all
* busses. To improve performance, if the current device
* is the same as the last device accessed, we don't touch the
* tlb.
*/
if (first_cfg) {
/* reserve a wired entry for pci config accesses */
first_cfg = 0;
pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
if (!pci_cfg_vm)
panic(KERN_ERR "PCI unable to get vm area\n");
pci_cfg_wired_entry = read_c0_wired();
add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
last_entryLo0 = last_entryLo1 = 0xffffffff;
}
/* Allow board vendors to implement their own off-chip idsel.
* If it doesn't succeed, may as well bail out at this point.
*/
@ -144,9 +140,12 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
/* page boundary */
cfg_base = cfg_base & PAGE_MASK;
/*
* To improve performance, if the current device is the same as
* the last device accessed, we don't touch the TLB.
*/
entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
(unsigned long)pci_cfg_vm->addr, PM_4K);

7
arch/mips/pci/ops-mace.c
View File

@ -42,6 +42,10 @@ static int
mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
u32 control = mace->pci.control;
/* disable master aborts interrupts during config read */
mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
*val = mace->pci.config_data.l;
break;
}
/* ack possible master abort */
mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
mace->pci.control = control;
DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);

4
arch/mips/pci/pci-ip32.c
View File

@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
.io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
};
static int __init mace_init(void)
@ -135,7 +136,8 @@ static int __init mace_init(void)
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
iomem_resource = mace_pci_mem_resource;
/* extend memory resources */
iomem_resource.end = mace_pci_mem_resource.end;
ioport_resource = mace_pci_io_resource;
register_pci_controller(&mace_pci_controller);

1
arch/mips/sgi-ip32/ip32-irq.c
View File

@ -426,7 +426,6 @@ static void ip32_irq0(void)
crime_int = crime->istat & crime_mask;
irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
crime_int = 1 << irq;
if (crime_int & CRIME_MACEISA_INT_MASK) {
unsigned long mace_int = mace->perif.ctrl.istat;

20
arch/mips/sgi-ip32/ip32-platform.c
View File

@ -13,21 +13,22 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
/*
* .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
*/
#define MACE_PORT(int) \
#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
#define MACE_PORT(offset,_irq) \
{ \
.irq = int, \
.mapbase = MACE_BASE + offset, \
.irq = _irq, \
.uartclk = 1843200, \
.iotype = UPIO_MEM, \
.flags = UPF_SKIP_TEST, \
.flags = UPF_SKIP_TEST|UPF_IOREMAP, \
.regshift = 8, \
}
static struct plat_serial8250_port uart8250_data[] = {
MACE_PORT(MACEISA_SERIAL1_IRQ),
MACE_PORT(MACEISA_SERIAL2_IRQ),
MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
{ },
};
@ -41,9 +42,6 @@ static struct platform_device uart8250_device = {
static int __init uart8250_init(void)
{
uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1;
uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2;
return platform_device_register(&uart8250_device);
}