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drm/i915: Implement WaSwitchSolVfFArbitrationPriority

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Bspec mentions this for HSW+. I can't quite tell what the effects are,
and I don't easily have a way to test this.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ben Widawsky 2013-03-20 14:49:14 -07:00 committed by Daniel Vetter
parent 96b219fac3
commit e3dff58550
2 changed files with 4 additions and 0 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
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@ -121,6 +121,7 @@
#define GAM_ECOCHK 0x4090 #define GAM_ECOCHK 0x4090
#define ECOCHK_SNB_BIT (1<<10) #define ECOCHK_SNB_BIT (1<<10)
#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
#define ECOCHK_PPGTT_CACHE64B (0x3<<3) #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
#define ECOCHK_PPGTT_CACHE4B (0x0<<3) #define ECOCHK_PPGTT_CACHE4B (0x0<<3)

3
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3770,6 +3770,9 @@ static void haswell_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
GEN6_MBCTL_ENABLE_BOOT_FETCH); GEN6_MBCTL_ENABLE_BOOT_FETCH);
/* WaSwitchSolVfFArbitrationPriority */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
/* XXX: This is a workaround for early silicon revisions and should be /* XXX: This is a workaround for early silicon revisions and should be
* removed later. * removed later.
*/ */