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ARM: davinci: dm644x: fix out range signal for ED

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Fix the video clock setting when custom timings are used with
pclock <= 27MHz. Existing video clock selection uses PLL2 mode
which results in a 54MHz clock whereas using the MXI mode results
in a 27MHz clock (which is the one actually desired).

This bug affects the Enhanced Definition (ED) support on DM644x.
Without this patch, out-range signals errors are were observed on
the TV when viewing ED. An out-of-range signal is often caused when
the field rate is above the rate that the television will handle.

Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>
[nsekhar@ti.com: reword commit message based on on-list discussion]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Lad, Prabhakar 2012-10-03 12:05:00 +05:30 committed by Sekhar Nori
parent f4a75d2eb7
commit e37212aa5d
1 changed files with 1 additions and 2 deletions
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3
arch/arm/mach-davinci/dm644x.c
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@ -713,8 +713,7 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
break; break;
case VPBE_ENC_CUSTOM_TIMINGS: case VPBE_ENC_CUSTOM_TIMINGS:
if (pclock <= 27000000) { if (pclock <= 27000000) {
v |= DM644X_VPSS_MUXSEL_PLL2_MODE | v |= DM644X_VPSS_DACCLKEN;
DM644X_VPSS_DACCLKEN;
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
} else { } else {
/* /*