renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-11-27 20:13:57 +08:00
Code

ARM: SoC fixes for 3.18-rc5

Browse Source 
Another small set of fixes:
 
 - Some DT compatible typo fixes
 - irq setup fix dealing with irq storms on orion
 - i2c quirk generalization for mvebu
 - A handful of smaller fixes for OMAP
 - A couple of added file patterns for OMAP entries in MAINTAINERS
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUaTBRAAoJEIwa5zzehBx3+wYP/iTZRQpaYuo3zw55oyYhyeUZ
 oh530Fz9ItyMi8rcGl4Tf0hh4tcdhYkpB2nCBgQ4x7FexyLvd2ZubLXOwwOnVter
 D+pVjpxdBuKtCdYm1+x35Zk6efbOYtJ7UDE1cGUQP+zA56Rx0K935/vlKZVkxJ19
 ytEksAna7z9PR4wR/YhYpMdcAxa7YXm7qnlU9gLx56MPBzUN5yvTP9bXs1qBOgPw
 ZC18uunr3RNIcmqEui+SEsCiDflkAe3xbwKvnsCmvQsyDsKYRmtuPOK8B86c9K9b
 LWedSG36/bcxb6IG/McAcqYgtReAUz0KkxvXu3SsAbWOLnzWPCgDUSgbvAtFt1Oz
 qtYPNNqqEC9fpiJE2LKJopK83+p5tYZ+MrJjGsqtIUJhLBW5xFs77NkrMDyEJJyN
 T+6GDDWk1UsMI49MRb1Nw6GTKmJvcOr0V3+OyHdjAOYqTbSeToOr5HHzCVYqhBTy
 fN3syzZKPAjXddAl70ixEy2o9CLckUBBrSrMyIEfENCAP74w+tc3UHFIv0yGmyDb
 95I5dfX2mvb/rxckQLOW7ewjp4DPAq7Kdo6+CBR39TJUEolweNQlUcZHQccalS6I
 cQ/SnVCYTQkIMFIhPrQQnL6/Yvwj/Qo+wu/hJL+3f4XKOKEQ88QpgCgVwKVN9Scg
 nBsEM2n2IbLPwuzAkvdv
 =0RR/
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Another small set of fixes:

   - some DT compatible typo fixes
   - irq setup fix dealing with irq storms on orion
   - i2c quirk generalization for mvebu
   - a handful of smaller fixes for OMAP
   - a couple of added file patterns for OMAP entries in MAINTAINERS"

* tag 'armsoc-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: at91/dt: Fix sama5d3x typos
  pinctrl: dra: dt-bindings: Fix output pull up/down
  MAINTAINERS: Update entry for omap related .dts files to cover new SoCs
  MAINTAINERS: add more files under OMAP SUPPORT
  ARM: dts: AM437x-SK-EVM: Fix DCDC3 voltage
  ARM: dts: AM437x-GP-EVM: Fix DCDC3 voltage
  ARM: dts: AM43x-EPOS-EVM: Fix DCDC3 voltage
  ARM: dts: am335x-evm: Fix 5th NAND partition's name
  ARM: orion: Fix for certain sequence of request_irq can cause irq storm
  ARM: mvebu: armada xp: Generalize use of i2c quirk
This commit is contained in:
Linus Torvalds 2014-11-16 16:21:57 -08:00
commit e35c5a2759
14 changed files with 68 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
MAINTAINERS
View File

@ -6611,6 +6611,23 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
S: Maintained
F: arch/arm/*omap*/
F: drivers/i2c/busses/i2c-omap.c
F: drivers/irqchip/irq-omap-intc.c
F: drivers/mfd/*omap*.c
F: drivers/mfd/menelaus.c
F: drivers/mfd/palmas.c
F: drivers/mfd/tps65217.c
F: drivers/mfd/tps65218.c
F: drivers/mfd/tps65910.c
F: drivers/mfd/twl-core.[ch]
F: drivers/mfd/twl4030*.c
F: drivers/mfd/twl6030*.c
F: drivers/mfd/twl6040*.c
F: drivers/regulator/palmas-regulator*.c
F: drivers/regulator/pbias-regulator.c
F: drivers/regulator/tps65217-regulator.c
F: drivers/regulator/tps65218-regulator.c
F: drivers/regulator/tps65910-regulator.c
F: drivers/regulator/twl-regulator.c
F: include/linux/i2c-omap.h
OMAP DEVICE TREE SUPPORT
@ -6621,6 +6638,9 @@ L: devicetree@vger.kernel.org
S: Maintained
F: arch/arm/boot/dts/*omap*
F: arch/arm/boot/dts/*am3*
F: arch/arm/boot/dts/*am4*
F: arch/arm/boot/dts/*am5*
F: arch/arm/boot/dts/*dra7*
OMAP CLOCK FRAMEWORK SUPPORT
M: Paul Walmsley <paul@pwsan.com>

2
arch/arm/boot/dts/am335x-evm.dts
View File

@ -489,7 +489,7 @@
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl";
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {

4
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -291,8 +291,8 @@
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdcdc3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};

4
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -363,8 +363,8 @@
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdds_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};

4
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -358,8 +358,8 @@
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdcdc3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};

2
arch/arm/boot/dts/sama5d31.dtsi
View File

@ -12,5 +12,5 @@
#include "sama5d3_uart.dtsi"
/ {
compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
};

2
arch/arm/boot/dts/sama5d33.dtsi
View File

@ -10,5 +10,5 @@
#include "sama5d3_gmac.dtsi"
/ {
compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
};

2
arch/arm/boot/dts/sama5d34.dtsi
View File

@ -12,5 +12,5 @@
#include "sama5d3_mci2.dtsi"
/ {
compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
};

2
arch/arm/boot/dts/sama5d35.dtsi
View File

@ -14,5 +14,5 @@
#include "sama5d3_tcb1.dtsi"
/ {
compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
};

2
arch/arm/boot/dts/sama5d36.dtsi
View File

@ -16,5 +16,5 @@
#include "sama5d3_uart.dtsi"
/ {
compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
};

2
arch/arm/boot/dts/sama5d3xcm.dtsi
View File

@ -8,7 +8,7 @@
*/
/ {
compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";

2
arch/arm/mach-mvebu/board-v7.c
View File

@ -188,7 +188,7 @@ static void __init thermal_quirk(void)
static void __init mvebu_dt_init(void)
{
if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
if (of_machine_is_compatible("marvell,armadaxp"))
i2c_quirk();
if (of_machine_is_compatible("marvell,a375-db")) {
external_abort_quirk();

36
arch/arm/plat-orion/gpio.c
View File

@ -497,6 +497,34 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
#define orion_gpio_dbg_show NULL
#endif
static void orion_gpio_unmask_irq(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
u32 reg_val;
u32 mask = d->mask;
irq_gc_lock(gc);
reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
reg_val |= mask;
irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
irq_gc_unlock(gc);
}
static void orion_gpio_mask_irq(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
u32 mask = d->mask;
u32 reg_val;
irq_gc_lock(gc);
reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
reg_val &= ~mask;
irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
irq_gc_unlock(gc);
}
void __init orion_gpio_init(struct device_node *np,
int gpio_base, int ngpio,
void __iomem *base, int mask_offset,
@ -565,8 +593,8 @@ void __init orion_gpio_init(struct device_node *np,
ct = gc->chip_types;
ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_mask = orion_gpio_mask_irq;
ct->chip.irq_unmask = orion_gpio_unmask_irq;
ct->chip.irq_set_type = gpio_irq_set_type;
ct->chip.name = ochip->chip.label;
@ -575,8 +603,8 @@ void __init orion_gpio_init(struct device_node *np,
ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
ct->chip.irq_ack = irq_gc_ack_clr_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_mask = orion_gpio_mask_irq;
ct->chip.irq_unmask = orion_gpio_unmask_irq;
ct->chip.irq_set_type = gpio_irq_set_type;
ct->handler = handle_edge_irq;
ct->chip.name = ochip->chip.label;

4
include/dt-bindings/pinctrl/dra.h
View File

@ -40,8 +40,8 @@
/* Active pin states */
#define PIN_OUTPUT (0 | PULL_DIS)
#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
#define PIN_OUTPUT_PULLUP (PULL_UP)
#define PIN_OUTPUT_PULLDOWN (0)
#define PIN_INPUT (INPUT_EN | PULL_DIS)
#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)