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bnx2: Flush the register writes which setup the MSI-X table
The MSI-X table size needs to be properly set before pci_enable_msix() is called. But on certain machines, the writes are delayed and the MSI-X table size is incorrectly read. By reading the BNX2_PCI_MSIX_CONTROL register, the writes are flushed and now ensure that the MSI-X table is set correctly before MSI-X is enable on the device. This patch was originally diagnosed and authored by Kalyan Ram Chintalapati <kalyanc@vmware.com>. Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Kalyan Ram Chintalapati <kalyanc@vmware.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -6145,6 +6145,10 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
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REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
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REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
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/* Need to flush the previous three writes to ensure MSI-X
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* is setup properly */
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REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
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for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
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msix_ent[i].entry = i;
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msix_ent[i].vector = 0;
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