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https://github.com/edk2-porting/linux-next.git
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regulator: qcom-spmi: Add vendor specific configuration
Add support for over current protection (OCP), pin control selection, soft start strength, and auto-mode. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Stephen Boyd
Mark Brown
parent
41dae91a72
commit
e2adfacde6
@ -91,13 +91,65 @@ see regulator.txt - with additional custom properties described below:
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- regulator-initial-mode:
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Usage: optional
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Value type: <u32>
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Descrption: 1 = Set initial mode to high power mode (HPM), also referred
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to as NPM. HPM consumes more ground current than LPM, but
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Description: 2 = Set initial mode to auto mode (automatically select
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between HPM and LPM); not available on boost type
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regulators.
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1 = Set initial mode to high power mode (HPM), also referred
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to as NPM. HPM consumes more ground current than LPM, but
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it can source significantly higher load current. HPM is not
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available on boost type regulators. For voltage switch type
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regulators, HPM implies that over current protection and
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soft start are active all the time. 0 = Set initial mode to
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low power mode (LPM).
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soft start are active all the time.
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0 = Set initial mode to low power mode (LPM).
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- qcom,ocp-max-retries:
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Usage: optional
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Value type: <u32>
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Description: Maximum number of times to try toggling a voltage switch
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off and back on as a result of consecutive over current
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events.
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- qcom,ocp-retry-delay:
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Usage: optional
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Value type: <u32>
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Description: Time to delay in milliseconds between each voltage switch
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toggle after an over current event takes place.
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- qcom,pin-ctrl-enable:
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Usage: optional
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Value type: <u32>
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Description: Bit mask specifying which hardware pins should be used to
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enable the regulator, if any; supported bits are:
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0 = ignore all hardware enable signals
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BIT(0) = follow HW0_EN signal
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BIT(1) = follow HW1_EN signal
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BIT(2) = follow HW2_EN signal
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BIT(3) = follow HW3_EN signal
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- qcom,pin-ctrl-hpm:
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Usage: optional
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Value type: <u32>
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Description: Bit mask specifying which hardware pins should be used to
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force the regulator into high power mode, if any;
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supported bits are:
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0 = ignore all hardware enable signals
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BIT(0) = follow HW0_EN signal
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BIT(1) = follow HW1_EN signal
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BIT(2) = follow HW2_EN signal
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BIT(3) = follow HW3_EN signal
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BIT(4) = follow PMIC awake state
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- qcom,vs-soft-start-strength:
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Usage: optional
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Value type: <u32>
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Description: This property sets the soft start strength for voltage
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switch type regulators; supported values are:
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0 = 0.05 uA
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1 = 0.25 uA
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2 = 0.55 uA
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3 = 0.75 uA
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Example:
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@ -26,6 +26,70 @@
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#include <linux/regmap.h>
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#include <linux/list.h>
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/* Pin control enable input pins. */
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
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#define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
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/* Pin control high power mode input pins. */
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#define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
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#define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
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#define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
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#define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
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#define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
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#define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
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#define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
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/*
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* Used with enable parameters to specify that hardware default register values
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* should be left unaltered.
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*/
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#define SPMI_REGULATOR_USE_HW_DEFAULT 2
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/* Soft start strength of a voltage switch type regulator */
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enum spmi_vs_soft_start_str {
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SPMI_VS_SOFT_START_STR_0P05_UA = 0,
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SPMI_VS_SOFT_START_STR_0P25_UA,
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SPMI_VS_SOFT_START_STR_0P55_UA,
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SPMI_VS_SOFT_START_STR_0P75_UA,
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SPMI_VS_SOFT_START_STR_HW_DEFAULT,
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};
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/**
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* struct spmi_regulator_init_data - spmi-regulator initialization data
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* @pin_ctrl_enable: Bit mask specifying which hardware pins should be
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* used to enable the regulator, if any
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* Value should be an ORing of
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* SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If
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* the bit specified by
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* SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
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* set, then pin control enable hardware registers
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* will not be modified.
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* @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
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* used to force the regulator into high power
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* mode, if any
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* Value should be an ORing of
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* SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If
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* the bit specified by
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* SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
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* set, then pin control mode hardware registers
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* will not be modified.
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* @vs_soft_start_strength: This parameter sets the soft start strength for
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* voltage switch type regulators. Its value
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* should be one of SPMI_VS_SOFT_START_STR_*. If
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* its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
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* then the soft start strength will be left at its
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* default hardware value.
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*/
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struct spmi_regulator_init_data {
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unsigned pin_ctrl_enable;
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unsigned pin_ctrl_hpm;
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enum spmi_vs_soft_start_str vs_soft_start_strength;
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};
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/* These types correspond to unique register layouts. */
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enum spmi_regulator_logical_type {
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SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
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@ -458,6 +522,14 @@ static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
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return spmi_regulator_common_enable(rdev);
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}
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static int spmi_regulator_vs_ocp(struct regulator_dev *rdev)
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{
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struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
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u8 reg = SPMI_VS_OCP_OVERRIDE;
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return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1);
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}
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static int spmi_regulator_common_disable(struct regulator_dev *rdev)
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{
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struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
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@ -791,6 +863,9 @@ static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
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if (reg & SPMI_COMMON_MODE_HPM_MASK)
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return REGULATOR_MODE_NORMAL;
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if (reg & SPMI_COMMON_MODE_AUTO_MASK)
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return REGULATOR_MODE_FAST;
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return REGULATOR_MODE_IDLE;
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}
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@ -798,11 +873,13 @@ static int
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spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
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{
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struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
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u8 mask = SPMI_COMMON_MODE_HPM_MASK;
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u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
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u8 val = 0;
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if (mode == REGULATOR_MODE_NORMAL)
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val = mask;
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val = SPMI_COMMON_MODE_HPM_MASK;
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else if (mode == REGULATOR_MODE_FAST)
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val = SPMI_COMMON_MODE_AUTO_MASK;
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return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
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}
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@ -972,6 +1049,7 @@ static struct regulator_ops spmi_vs_ops = {
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.is_enabled = spmi_regulator_common_is_enabled,
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.set_pull_down = spmi_regulator_common_set_pull_down,
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.set_soft_start = spmi_regulator_common_set_soft_start,
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.set_over_current_protection = spmi_regulator_vs_ocp,
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};
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static struct regulator_ops spmi_boost_ops = {
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@ -1202,10 +1280,111 @@ static int spmi_regulator_ftsmps_init_slew_rate(struct spmi_regulator *vreg)
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return ret;
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}
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static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
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const struct spmi_regulator_init_data *data)
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{
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int ret;
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enum spmi_regulator_logical_type type;
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u8 ctrl_reg[8], reg, mask;
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type = vreg->logical_type;
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ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
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if (ret)
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return ret;
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/* Set up enable pin control. */
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if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS
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|| type == SPMI_REGULATOR_LOGICAL_TYPE_LDO
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|| type == SPMI_REGULATOR_LOGICAL_TYPE_VS)
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&& !(data->pin_ctrl_enable
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& SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
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ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
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~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
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ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
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data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
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}
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/* Set up mode pin control. */
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if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS
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|| type == SPMI_REGULATOR_LOGICAL_TYPE_LDO)
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&& !(data->pin_ctrl_hpm
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& SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
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ctrl_reg[SPMI_COMMON_IDX_MODE] &=
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~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
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ctrl_reg[SPMI_COMMON_IDX_MODE] |=
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data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
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}
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if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS
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&& !(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
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ctrl_reg[SPMI_COMMON_IDX_MODE] &=
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~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
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ctrl_reg[SPMI_COMMON_IDX_MODE] |=
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data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
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}
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if ((type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS
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|| type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS
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|| type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO)
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&& !(data->pin_ctrl_hpm
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& SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
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ctrl_reg[SPMI_COMMON_IDX_MODE] &=
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~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
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ctrl_reg[SPMI_COMMON_IDX_MODE] |=
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data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
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}
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/* Write back any control register values that were modified. */
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ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
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if (ret)
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return ret;
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/* Set soft start strength and over current protection for VS. */
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if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
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if (data->vs_soft_start_strength
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!= SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
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reg = data->vs_soft_start_strength
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& SPMI_VS_SOFT_START_SEL_MASK;
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mask = SPMI_VS_SOFT_START_SEL_MASK;
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return spmi_vreg_update_bits(vreg,
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SPMI_VS_REG_SOFT_START,
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reg, mask);
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}
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}
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return 0;
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}
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static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
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struct device_node *node, struct spmi_regulator_init_data *data)
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{
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/*
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* Initialize configuration parameters to use hardware default in case
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* no value is specified via device tree.
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*/
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data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
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data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
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data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT;
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/* These bindings are optional, so it is okay if they aren't found. */
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of_property_read_u32(node, "qcom,ocp-max-retries",
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&vreg->ocp_max_retries);
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of_property_read_u32(node, "qcom,ocp-retry-delay",
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&vreg->ocp_retry_delay_ms);
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of_property_read_u32(node, "qcom,pin-ctrl-enable",
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&data->pin_ctrl_enable);
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of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
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of_property_read_u32(node, "qcom,vs-soft-start-strength",
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&data->vs_soft_start_strength);
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}
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static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
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{
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if (mode)
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if (mode == 1)
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return REGULATOR_MODE_NORMAL;
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if (mode == 2)
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return REGULATOR_MODE_FAST;
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return REGULATOR_MODE_IDLE;
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}
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@ -1214,12 +1393,23 @@ static int spmi_regulator_of_parse(struct device_node *node,
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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struct spmi_regulator_init_data data = { };
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struct spmi_regulator *vreg = config->driver_data;
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struct device *dev = config->dev;
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int ret;
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vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
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vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
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spmi_regulator_get_dt_config(vreg, node, &data);
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if (!vreg->ocp_max_retries)
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vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
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if (!vreg->ocp_retry_delay_ms)
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vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
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ret = spmi_regulator_init_registers(vreg, &data);
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if (ret) {
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dev_err(dev, "common initialization failed, ret=%d\n", ret);
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return ret;
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}
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if (vreg->logical_type == SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS) {
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ret = spmi_regulator_ftsmps_init_slew_rate(vreg);
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