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drm: meson: global clean-up
This patch aims to: - Add general and TODO comments - Respect coding style for multi-line comments - Align macro definitions - Remove useless macro Signed-off-by: Julien Masson <jmasson@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/86pnn382e8.fsf@baylibre.com
This commit is contained in:
Julien Masson
Neil Armstrong
parent
7eef9e6104
commit
e101214124
@ -429,6 +429,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3, 0x3);
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/* Enable cec_clk and hdcp22_tmdsclk_en */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3 << 4, 0x3 << 4);
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@ -100,7 +100,8 @@
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#define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6)
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#define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7)
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/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
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/*
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* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
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* 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
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* Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
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* every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
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@ -135,7 +136,8 @@
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/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
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#define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B)
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/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
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/*
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* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
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* used when TMDS CLK rate = TMDS character rate /4. Default 0.
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* Bit 0 R Reserved. Default 0.
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* [ 1] shift_tmds_clk_pttn
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@ -143,12 +145,14 @@
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*/
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#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C)
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/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
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/*
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* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
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* failure, write 1 to clear the failure flag. Default 0.
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*/
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#define HDMITX_TOP_REVOCMEM_STAT (0x00D)
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/* Bit 1 R filtered RxSense status
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/*
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* Bit 1 R filtered RxSense status
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* Bit 0 R filtered HPD status.
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*/
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#define HDMITX_TOP_STAT0 (0x00E)
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@ -398,19 +398,19 @@
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#define VPP_PREBLEND_CURRENT_XY 0x1d24
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#define VPP_POSTBLEND_CURRENT_XY 0x1d25
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#define VPP_MISC 0x1d26
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#define VPP_PREBLEND_ENABLE BIT(6)
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#define VPP_POSTBLEND_ENABLE BIT(7)
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#define VPP_OSD2_ALPHA_PREMULT BIT(8)
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#define VPP_OSD1_ALPHA_PREMULT BIT(9)
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#define VPP_VD1_POSTBLEND BIT(10)
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#define VPP_VD2_POSTBLEND BIT(11)
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#define VPP_OSD1_POSTBLEND BIT(12)
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#define VPP_OSD2_POSTBLEND BIT(13)
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#define VPP_VD1_PREBLEND BIT(14)
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#define VPP_VD2_PREBLEND BIT(15)
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#define VPP_OSD1_PREBLEND BIT(16)
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#define VPP_OSD2_PREBLEND BIT(17)
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#define VPP_COLOR_MNG_ENABLE BIT(28)
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#define VPP_PREBLEND_ENABLE BIT(6)
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#define VPP_POSTBLEND_ENABLE BIT(7)
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#define VPP_OSD2_ALPHA_PREMULT BIT(8)
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#define VPP_OSD1_ALPHA_PREMULT BIT(9)
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#define VPP_VD1_POSTBLEND BIT(10)
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#define VPP_VD2_POSTBLEND BIT(11)
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#define VPP_OSD1_POSTBLEND BIT(12)
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#define VPP_OSD2_POSTBLEND BIT(13)
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#define VPP_VD1_PREBLEND BIT(14)
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#define VPP_VD2_PREBLEND BIT(15)
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#define VPP_OSD1_PREBLEND BIT(16)
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#define VPP_OSD2_PREBLEND BIT(17)
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#define VPP_COLOR_MNG_ENABLE BIT(28)
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#define VPP_OFIFO_SIZE 0x1d27
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#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0)
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#define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000)
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@ -621,6 +621,7 @@
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#define OSD34_SCI_WH_M1 0x3d29
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#define OSD34_SCO_H_START_END 0x3d2a
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#define OSD34_SCO_V_START_END 0x3d2b
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/* viu2 */
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#define VIU2_ADDR_START 0x1e00
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#define VIU2_ADDR_END 0x1eff
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@ -1603,7 +1604,6 @@
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#define OSD1_AFBCD_STATUS 0x31a8
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#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9
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#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa
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#define VIU_MISC_CTRL1 0x1a07
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/* add for gxm and 962e dv core2 */
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#define DOLBY_CORE2A_SWAP_CTRL1 0x3434
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@ -1618,8 +1618,6 @@
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#define VPU_MAFBC_COMMAND 0x3a05
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#define VPU_MAFBC_STATUS 0x3a06
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#define VPU_MAFBC_SURFACE_CFG 0x3a07
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/* osd afbc on g12a */
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#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10
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#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11
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#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
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@ -1740,6 +1738,5 @@
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#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
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#define VPP_RDARB_MODE 0x3978
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#define VPP_RDARB_REQEN_SLV 0x3979
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#define VPU_RDARB_MODE_L2C1 0x279d
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#endif /* __MESON_REGISTERS_H */
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@ -496,6 +496,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
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/* Enable and reset */
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/* TODO: add specific macro for g12a here */
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regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
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0x3 << 28, 0x3 << 28);
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@ -970,7 +971,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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meson_venci_cvbs_clock_config(priv);
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return;
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} else if (target == MESON_VCLK_TARGET_DMT) {
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/* The DMT clock path is fixed after the PLL:
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/*
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* The DMT clock path is fixed after the PLL:
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* - automatic PLL freq + OD management
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* - vid_pll_div = VID_PLL_DIV_5
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* - vclk_div = 2
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@ -61,9 +61,9 @@
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/* HHI Registers */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
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#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
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#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
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struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
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@ -1085,7 +1085,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
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writel_relaxed(vmode->enci.video_mode,
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priv->io_base + _REG(ENCI_VIDEO_MODE));
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/* Advanced Video Mode :
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/*
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* Advanced Video Mode :
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* Demux shifting 0x2
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* Blank line end at line17/22
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* High bandwidth Luma Filter
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@ -1599,7 +1600,8 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
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writel_relaxed(mode->video_mode,
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priv->io_base + _REG(ENCI_VIDEO_MODE));
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/* Advanced Video Mode :
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/*
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* Advanced Video Mode :
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* Demux shifting 0x2
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* Blank line end at line17/22
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* High bandwidth Luma Filter
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