mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 05:04:00 +08:00
ARM: DRA7: hwmod: Add OCP2SCP3 module
This module is needed for the SATA and PCIe PHYs. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
509efaf3d1
commit
df0d0f11ff
@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/* ocp2scp3 */
|
||||
static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
|
||||
.name = "ocp2scp3",
|
||||
.class = &dra7xx_ocp2scp_hwmod_class,
|
||||
.clkdm_name = "l3init_clkdm",
|
||||
.main_clk = "l4_root_clk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'qspi' class
|
||||
*
|
||||
@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> ocp2scp3 */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_ocp2scp3_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4b300000,
|
||||
@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l4_per1__mmc4,
|
||||
&dra7xx_l4_cfg__mpu,
|
||||
&dra7xx_l4_cfg__ocp2scp1,
|
||||
&dra7xx_l4_cfg__ocp2scp3,
|
||||
&dra7xx_l3_main_1__qspi,
|
||||
&dra7xx_l4_cfg__sata,
|
||||
&dra7xx_l4_cfg__smartreflex_core,
|
||||
|
Loading…
Reference in New Issue
Block a user