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https://github.com/edk2-porting/linux-next.git
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Merge branch 'clk-ux500' into clk-next
* clk-ux500: clk: ux500: Convert ABx500 clocks to use OF probing clk: ux500: Add device tree bindings for ABx500 clocks clk: ux500: move AB8500 sysclk over to PRCMU clk driver
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commit
de9b5a2404
@ -0,0 +1,20 @@
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Clock bindings for ST-Ericsson ABx500 clocks
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Required properties :
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- compatible : shall contain the following:
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"stericsson,ab8500-clk"
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- #clock-cells should be <1>
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The ABx500 clocks need to be placed as a subnode of an AB8500
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device node, see mfd/ab8500.txt
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/ste-ab8500.h header and can be used in device
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tree sources.
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Example:
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clock-controller {
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compatible = "stericsson,ab8500-clk";
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#clock-cells = <1>;
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};
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@ -10,20 +10,26 @@
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/abx500/ab8500.h>
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#include <linux/mfd/abx500/ab8500-sysctrl.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/mfd/dbx500-prcmu.h>
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#include <dt-bindings/clock/ste-ab8500.h>
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#include "clk.h"
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#define AB8500_NUM_CLKS 6
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static struct clk *ab8500_clks[AB8500_NUM_CLKS];
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static struct clk_onecell_data ab8500_clk_data;
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/* Clock definitions for ab8500 */
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static int ab8500_reg_clks(struct device *dev)
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{
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int ret;
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struct clk *clk;
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struct device_node *np = dev->of_node;
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const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
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u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
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u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
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@ -32,55 +38,52 @@ static int ab8500_reg_clks(struct device *dev)
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(1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
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};
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dev_info(dev, "register clocks for ab850x\n");
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/* Enable SWAT */
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ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
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if (ret)
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return ret;
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/* ab8500_sysclk */
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clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
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clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
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clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
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clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
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clk_register_clkdev(clk, "sysclk", "shrm_bus");
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/* ab8500_sysclk2 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
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clk_register_clkdev(clk, "sysclk", "0-0070");
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ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
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/* ab8500_sysclk3 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
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clk_register_clkdev(clk, "sysclk", "cg1960_core.0");
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ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
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/* ab8500_sysclk4 */
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clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
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AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
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ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
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/* ab_ulpclk */
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clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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38400000, 9000, 0);
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clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0");
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ab8500_clks[AB8500_SYSCLK_ULP] = clk;
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/* ab8500_intclk */
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clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
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intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
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clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0");
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clk_register_clkdev(clk, NULL, "ab8500-pwm.1");
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ab8500_clks[AB8500_SYSCLK_INT] = clk;
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/* ab8500_audioclk */
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clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
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AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
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clk_register_clkdev(clk, "audioclk", "ab8500-codec.0");
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ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
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ab8500_clk_data.clks = ab8500_clks;
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ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
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of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
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dev_info(dev, "registered clocks for ab850x\n");
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return 0;
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}
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@ -116,9 +119,15 @@ static int abx500_clk_probe(struct platform_device *pdev)
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return ret;
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}
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static const struct of_device_id abx500_clk_match[] = {
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{ .compatible = "stericsson,ab8500-clk", },
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{}
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};
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static struct platform_driver abx500_clk_driver = {
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.driver = {
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.name = "abx500-clk",
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.of_match_table = abx500_clk_match,
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},
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.probe = abx500_clk_probe,
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};
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@ -127,7 +136,6 @@ static int __init abx500_clk_init(void)
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{
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return platform_driver_register(&abx500_clk_driver);
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}
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arch_initcall(abx500_clk_init);
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MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
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@ -206,6 +206,9 @@ static void u8500_clk_init(struct device_node *np)
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clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
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prcmu_clk[PRCMU_TIMCLK] = clk;
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clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
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prcmu_clk[PRCMU_SYSCLK] = clk;
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clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
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100000000, CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_SDMMCCLK] = clk;
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11
include/dt-bindings/clock/ste-ab8500.h
Normal file
11
include/dt-bindings/clock/ste-ab8500.h
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@ -0,0 +1,11 @@
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#ifndef __STE_CLK_AB8500_H__
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#define __STE_CLK_AB8500_H__
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#define AB8500_SYSCLK_BUF2 0
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#define AB8500_SYSCLK_BUF3 1
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#define AB8500_SYSCLK_BUF4 2
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#define AB8500_SYSCLK_ULP 3
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#define AB8500_SYSCLK_INT 4
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#define AB8500_SYSCLK_AUDIO 5
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#endif
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