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drm/i915: fix regression due to ba3d8d749b
We don't track gpu flush request in any special way. So even with obj->write_domain == 0, a gpu flush might be outstanding but no yet executed. Even worse, the latest request might use the object only for reading. So and unconditional call to object_wait_rendering is needed for !pipelined. Hence revert that patch fully and untangle the flushing from the synchronization again. Reported-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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parent
ba84cd1f2b
commit
de18a29e0f
@ -38,8 +38,7 @@
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static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
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bool pipelined);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
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static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
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@ -2594,7 +2593,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
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if (reg->gpu) {
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int ret;
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ret = i915_gem_object_flush_gpu_write_domain(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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@ -2742,8 +2741,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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/** Flushes any GPU write domain for the object if it's dirty. */
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static int
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
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bool pipelined)
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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uint32_t old_write_domain;
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@ -2762,10 +2760,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
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obj->read_domains,
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old_write_domain);
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if (pipelined)
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return 0;
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return i915_gem_object_wait_rendering(obj, true);
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return 0;
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}
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/** Flushes the GTT write domain for the object if it's dirty. */
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@ -2826,18 +2821,15 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret != 0)
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return ret;
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ret = i915_gem_object_wait_rendering(obj, true);
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if (ret)
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return ret;
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i915_gem_object_flush_cpu_write_domain(obj);
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if (write) {
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ret = i915_gem_object_wait_rendering(obj, true);
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if (ret)
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return ret;
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}
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old_write_domain = obj->write_domain;
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old_read_domains = obj->read_domains;
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@ -2875,7 +2867,7 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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ret = i915_gem_object_flush_gpu_write_domain(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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@ -2924,9 +2916,12 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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uint32_t old_write_domain, old_read_domains;
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int ret;
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret != 0)
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return ret;
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ret = i915_gem_object_wait_rendering(obj, true);
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if (ret)
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return ret;
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i915_gem_object_flush_gtt_write_domain(obj);
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@ -2935,12 +2930,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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*/
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i915_gem_object_set_to_full_cpu_read_domain(obj);
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if (write) {
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ret = i915_gem_object_wait_rendering(obj, true);
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if (ret)
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return ret;
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}
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old_write_domain = obj->write_domain;
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old_read_domains = obj->read_domains;
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@ -3205,9 +3194,13 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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if (offset == 0 && size == obj->size)
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return i915_gem_object_set_to_cpu_domain(obj, 0);
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret != 0)
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return ret;
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ret = i915_gem_object_wait_rendering(obj, true);
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if (ret)
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return ret;
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i915_gem_object_flush_gtt_write_domain(obj);
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/* If we're already fully in the CPU read domain, we're done. */
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