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https://github.com/edk2-porting/linux-next.git
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ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM
This patch adds basic support for PHYTEC phyCORE-i.MX 6 SOM with i.MX 6Quad/Dual or i.MX 6DualLight/Solo. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Stefan Riedmueller
Shawn Guo
parent
dc5c632596
commit
ddec5d1c00
279
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
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279
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
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@ -0,0 +1,279 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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rtc1 = &da9062_rtc;
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rtc2 = &snvs_rtc;
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};
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/*
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* Set the minimum memory size here and
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* let the bootloader set the real size.
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*/
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x8000000>;
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};
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gpio_leds_som: somleds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioleds_som>;
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som-led-green {
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label = "phycore:green";
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gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
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status = "okay";
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m25p80: flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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status = "disabled";
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-handle = <ðphy>;
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phy-mode = "rgmii";
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phy-supply = <&vdd_eth_io>;
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phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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status = "disabled";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@3 {
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reg = <3>;
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txc-skew-ps = <1680>;
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rxc-skew-ps = <1860>;
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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status = "disabled";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <400000>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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pmic@58 {
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compatible = "dlg,da9062";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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reg = <0x58>;
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interrupt-parent = <&gpio1>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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da9062_rtc: rtc {
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compatible = "dlg,da9062-rtc";
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};
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watchdog {
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compatible = "dlg,da9062-watchdog";
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};
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regulators {
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vdd_arm: buck1 {
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <730000>;
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regulator-max-microvolt = <1380000>;
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regulator-always-on;
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};
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vdd_soc: buck2 {
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regulator-name = "vdd_soc";
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regulator-min-microvolt = <730000>;
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regulator-max-microvolt = <1380000>;
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regulator-always-on;
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};
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vdd_ddr3_1p5: buck3 {
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regulator-name = "vdd_ddr3";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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};
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vdd_eth_1p2: buck4 {
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regulator-name = "vdd_eth";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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vdd_snvs: ldo1 {
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regulator-name = "vdd_snvs";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vdd_high: ldo2 {
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regulator-name = "vdd_high";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vdd_eth_io: ldo3 {
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regulator-name = "vdd_eth_io";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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vdd_emmc_1p8: ldo4 {
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regulator-name = "vdd_emmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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};
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®_arm {
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vin-supply = <&vdd_arm>;
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};
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®_pu {
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vin-supply = <&vdd_soc>;
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};
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®_soc {
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vin-supply = <&vdd_soc>;
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};
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&snvs_poweroff {
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status = "okay";
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};
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&usdhc4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4>;
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bus-width = <8>;
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non-removable;
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vmmc-supply = <&vdd_emmc_1p8>;
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status = "disabled";
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};
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
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>;
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};
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pinctrl_gpioleds_som: gpioledssomgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
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MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
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>;
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};
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pinctrl_pmic: pmicgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
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>;
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};
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pinctrl_usdhc4: usdhc4grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
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MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
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MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
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MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
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MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
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>;
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};
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};
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