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arm64: cache: Identify VPIPT I-caches
Add support for detecting VPIPT I-caches, as introduced by ARMv8.2. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -25,6 +25,7 @@
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define ICACHE_POLICY_VPIPT 0
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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#define ICACHE_POLICY_PIPT 3
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@ -45,6 +46,7 @@
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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#define ICACHEF_ALIASING 0
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#define ICACHEF_ALIASING 0
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#define ICACHEF_VPIPT 1
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extern unsigned long __icache_flags;
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extern unsigned long __icache_flags;
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/*
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/*
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@ -56,6 +58,11 @@ static inline int icache_is_aliasing(void)
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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}
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static inline int icache_is_vpipt(void)
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{
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return test_bit(ICACHEF_VPIPT, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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static inline u32 cache_type_cwg(void)
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{
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{
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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@ -46,6 +46,7 @@ static char *icache_policy_str[] = {
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[0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
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[0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
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[ICACHE_POLICY_VIPT] = "VIPT",
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[ICACHE_POLICY_VIPT] = "VIPT",
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[ICACHE_POLICY_PIPT] = "PIPT",
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[ICACHE_POLICY_PIPT] = "PIPT",
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[ICACHE_POLICY_VPIPT] = "VPIPT",
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};
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};
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unsigned long __icache_flags;
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unsigned long __icache_flags;
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@ -291,6 +292,9 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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switch (l1ip) {
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switch (l1ip) {
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case ICACHE_POLICY_PIPT:
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case ICACHE_POLICY_PIPT:
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break;
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break;
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case ICACHE_POLICY_VPIPT:
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set_bit(ICACHEF_VPIPT, &__icache_flags);
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break;
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default:
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default:
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/* Fallthrough */
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/* Fallthrough */
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case ICACHE_POLICY_VIPT:
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case ICACHE_POLICY_VIPT:
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