mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-03 19:24:02 +08:00
ASoC: adsp: Set DSP clock rate to SYSCLK rate
For simplicity always run the DSP at the SYSCLK rate. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
parent
10a2b662c4
commit
dd49e2c8b9
@ -544,6 +544,28 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
|
|||||||
|
|
||||||
switch (event) {
|
switch (event) {
|
||||||
case SND_SOC_DAPM_POST_PMU:
|
case SND_SOC_DAPM_POST_PMU:
|
||||||
|
/*
|
||||||
|
* For simplicity set the DSP clock rate to be the
|
||||||
|
* SYSCLK rate rather than making it configurable.
|
||||||
|
*/
|
||||||
|
ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
|
||||||
|
if (ret != 0) {
|
||||||
|
adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
|
||||||
|
ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
val = (val & ARIZONA_SYSCLK_FREQ_MASK)
|
||||||
|
>> ARIZONA_SYSCLK_FREQ_SHIFT;
|
||||||
|
|
||||||
|
ret = regmap_update_bits(dsp->regmap,
|
||||||
|
dsp->base + ADSP2_CLOCKING,
|
||||||
|
ADSP2_CLK_SEL_MASK, val);
|
||||||
|
if (ret != 0) {
|
||||||
|
adsp_err(dsp, "Failed to set clock rate: %d\n",
|
||||||
|
ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
if (dsp->dvfs) {
|
if (dsp->dvfs) {
|
||||||
ret = regmap_read(dsp->regmap,
|
ret = regmap_read(dsp->regmap,
|
||||||
dsp->base + ADSP2_CLOCKING, &val);
|
dsp->base + ADSP2_CLOCKING, &val);
|
||||||
|
Loading…
Reference in New Issue
Block a user