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tile PCI RC: add dma_get_required_mask()

The standard kernel function dma_get_required_mask() uses the
highest DRAM address to determine if 32-bit or 64-bit DMA addressing
is needed.  This only works on architectures that have direct mapping
between the PA and the PCI address space, i.e. those that don't have
I/O TLBs or have I/O TLB but choose to use direct mapping.  Neither
of these are true for tilegx.  Whether to use 64-bit DMA should depend
on the PCI device's capability only, not on the amount of DRAM
installeds, so we now advertise a 64-bit DMA mask unconditionally.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf 2013-08-05 13:40:47 -04:00
parent 8d9e53b93d
commit dc7d5cf2ca
2 changed files with 22 additions and 0 deletions

View File

@ -20,6 +20,10 @@
#include <linux/cache.h>
#include <linux/io.h>
#ifdef __tilegx__
#define ARCH_HAS_DMA_GET_REQUIRED_MASK
#endif
extern struct dma_map_ops *tile_dma_map_ops;
extern struct dma_map_ops *gx_pci_dma_map_ops;
extern struct dma_map_ops *gx_legacy_pci_dma_map_ops;

View File

@ -607,3 +607,21 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
}
EXPORT_SYMBOL(dma_set_coherent_mask);
#endif
#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
/*
* The generic dma_get_required_mask() uses the highest physical address
* (max_pfn) to provide the hint to the PCI drivers regarding 32-bit or
* 64-bit DMA configuration. Since TILEGx has I/O TLB/MMU, allowing the
* DMAs to use the full 64-bit PCI address space and not limited by
* the physical memory space, we always let the PCI devices use
* 64-bit DMA if they have that capability, by returning the 64-bit
* DMA mask here. The device driver has the option to use 32-bit DMA if
* the device is not capable of 64-bit DMA.
*/
u64 dma_get_required_mask(struct device *dev)
{
return DMA_BIT_MASK(64);
}
EXPORT_SYMBOL_GPL(dma_get_required_mask);
#endif