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[media] dvb-frontends/stv0367: add Digital Devices compatibility
This - in conjunction with the previous changes - makes it possible to use the STV0367 DVB-C/T demodulator driver with Digital Devices hardware having this demodulator soldered on them (namely CineCTv6 bridges and some earlier DuoFlex CT addon modules). The changes do the following: - add a third *_attach function which will make use of a third frontend_ops struct which announces both -C and -T support (the same as with DD's own driver stv0367dd). This is necessary to support both delivery systems on one FE without having to do large conversions to VB2 or the need to select either -C or -T mode via modparams and the like. Additionally, the frontend_ops point to new "glue" functions which will then call into the existing functionality depending on the active delivery system/demod state (all used functionality works almost OOTB). - Demod initialisation has been ported from stv0367dd. DD's driver always does a full init of both OFDM and QAM cores, with some additional things. The active delivery system is remembered and upon switch, the Demod will be reconfigured to work in OFDM or QAM mode (that's what the ddb_setup_XX functions are used for). Note that in QAM mode, the DD demods work with an IC speed of 58Mhz. It's not very good to perform full reinits upon Demod mode changes since in very rare occasions this can lead to the I2C interface or the whole Demod to crash, requiring a powercycle, thus the flag to perform full reinit is set to disabled. - A little enum is added for named identifiers of the current Demod state. Initialisation code/register writes originate from stv0367dd. Permission to reuse was formally granted by Ralph Metzler <rjkm@metzlerbros.de>. Signed-off-by: Daniel Scheller <d.scheller@gmx.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Daniel Scheller
Mauro Carvalho Chehab
parent
2cafa6b288
commit
dbbac11e1d
@ -46,6 +46,8 @@ module_param_named(i2c_debug, i2cdebug, int, 0644);
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} while (0)
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/* DVB-C */
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enum active_demod_state { demod_none, demod_ter, demod_cab };
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struct stv0367cab_state {
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enum stv0367_cab_signal_type state;
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u32 mclk;
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@ -96,6 +98,7 @@ struct stv0367_state {
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u8 deftabs;
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u8 reinit_on_setfrontend;
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u8 auto_if_khz;
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enum active_demod_state activedemod;
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};
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#define RF_LOOKUP_TABLE_SIZE 31
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@ -2880,6 +2883,327 @@ error:
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}
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EXPORT_SYMBOL(stv0367cab_attach);
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/*
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* Functions for operation on Digital Devices hardware
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*/
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static void stv0367ddb_setup_ter(struct stv0367_state *state)
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{
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stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
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stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
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stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
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stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
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stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
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stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
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/* Tuner Setup */
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/* Buffer Q disabled, I Enabled, unsigned ADC */
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stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
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stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
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/* Clock setup */
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/* PLL bypassed and disabled */
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stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
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stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
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/* IC runs at 54 MHz with a 27 MHz crystal */
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stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
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msleep(50);
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/* PLL enabled and used */
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stv0367_writereg(state, R367TER_ANACTRL, 0x00);
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state->activedemod = demod_ter;
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}
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static void stv0367ddb_setup_cab(struct stv0367_state *state)
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{
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stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
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stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
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stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
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stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
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stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
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stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
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/* Tuner Setup */
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/* Buffer Q disabled, I Enabled, signed ADC */
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stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
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/* ADCQ disabled */
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stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
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/* Clock setup */
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/* PLL bypassed and disabled */
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stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
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/* Set QAM */
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stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
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/* IC runs at 58 MHz with a 27 MHz crystal */
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stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
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msleep(50);
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/* PLL enabled and used */
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stv0367_writereg(state, R367TER_ANACTRL, 0x00);
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state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
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state->config->xtal);
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state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
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state->config->xtal);
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state->activedemod = demod_cab;
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}
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static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
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{
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struct stv0367_state *state = fe->demodulator_priv;
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switch (fe->dtv_property_cache.delivery_system) {
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case SYS_DVBT:
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if (state->activedemod != demod_ter)
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stv0367ddb_setup_ter(state);
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return stv0367ter_set_frontend(fe);
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case SYS_DVBC_ANNEX_A:
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if (state->activedemod != demod_cab)
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stv0367ddb_setup_cab(state);
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/* protect against division error oopses */
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if (fe->dtv_property_cache.symbol_rate == 0) {
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printk(KERN_ERR "Invalid symbol rate\n");
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return -EINVAL;
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}
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return stv0367cab_set_frontend(fe);
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default:
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break;
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}
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return -EINVAL;
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}
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static int stv0367ddb_read_status(struct dvb_frontend *fe,
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enum fe_status *status)
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{
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struct stv0367_state *state = fe->demodulator_priv;
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switch (state->activedemod) {
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case demod_ter:
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return stv0367ter_read_status(fe, status);
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case demod_cab:
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return stv0367cab_read_status(fe, status);
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default:
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break;
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}
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return -EINVAL;
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}
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static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
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struct dtv_frontend_properties *p)
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{
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struct stv0367_state *state = fe->demodulator_priv;
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switch (state->activedemod) {
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case demod_ter:
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return stv0367ter_get_frontend(fe, p);
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case demod_cab:
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return stv0367cab_get_frontend(fe, p);
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default:
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break;
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}
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return -EINVAL;
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}
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static int stv0367ddb_sleep(struct dvb_frontend *fe)
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{
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struct stv0367_state *state = fe->demodulator_priv;
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switch (state->activedemod) {
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case demod_ter:
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state->activedemod = demod_none;
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return stv0367ter_sleep(fe);
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case demod_cab:
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state->activedemod = demod_none;
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return stv0367cab_sleep(fe);
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default:
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break;
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}
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return -EINVAL;
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}
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static int stv0367ddb_init(struct stv0367_state *state)
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{
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struct stv0367ter_state *ter_state = state->ter_state;
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stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
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if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
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stv0367_write_table(state,
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stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
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stv0367_write_table(state,
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stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
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stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
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stv0367_write_table(state,
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stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
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stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
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stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
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stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
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stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
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stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
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stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
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stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
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stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
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/* OFDM TS Setup */
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stv0367_writereg(state, R367TER_TSCFGH, 0x70);
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stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
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stv0367_writereg(state, R367TER_TSCFGL, 0x20);
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stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
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stv0367_writereg(state, R367TER_TSCFGH, 0x71);
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stv0367_writereg(state, R367TER_TSCFGH, 0x70);
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stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
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/* Also needed for QAM */
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stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
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stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
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/* QAM TS setup, note exact format also depends on descrambler */
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/* settings */
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/* Inverted Clock, Swap, serial */
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stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
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/* Clock setup (PLL bypassed and disabled) */
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stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
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/* IC runs at 58 MHz with a 27 MHz crystal */
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stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
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/* Tuner setup */
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/* Buffer Q disabled, I Enabled, signed ADC */
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stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
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stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
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/* Improves the C/N lock limit */
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stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
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/* ZIF/IF Automatic mode */
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stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
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/* Improving burst noise performances */
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stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
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/* Improving ACI performances */
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stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
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/* PLL enabled and used */
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stv0367_writereg(state, R367TER_ANACTRL, 0x00);
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stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
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ter_state->pBER = 0;
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ter_state->first_lock = 0;
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ter_state->unlock_counter = 2;
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return 0;
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}
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static const struct dvb_frontend_ops stv0367ddb_ops = {
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.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
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.info = {
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.name = "ST STV0367 DDB DVB-C/T",
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.frequency_min = 47000000,
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.frequency_max = 865000000,
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.frequency_stepsize = 166667,
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.frequency_tolerance = 0,
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.symbol_rate_min = 870000,
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.symbol_rate_max = 11700000,
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.caps = /* DVB-C */
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0x400 |/* FE_CAN_QAM_4 */
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FE_CAN_QAM_16 | FE_CAN_QAM_32 |
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FE_CAN_QAM_64 | FE_CAN_QAM_128 |
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FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
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/* DVB-T */
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FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
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FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
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FE_CAN_FEC_AUTO |
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FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
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FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
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FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
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FE_CAN_INVERSION_AUTO |
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FE_CAN_MUTE_TS
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},
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.release = stv0367_release,
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.sleep = stv0367ddb_sleep,
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.i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
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.set_frontend = stv0367ddb_set_frontend,
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.get_frontend = stv0367ddb_get_frontend,
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.get_tune_settings = stv0367_get_tune_settings,
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.read_status = stv0367ddb_read_status,
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};
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struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
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struct i2c_adapter *i2c)
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{
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struct stv0367_state *state = NULL;
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struct stv0367ter_state *ter_state = NULL;
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struct stv0367cab_state *cab_state = NULL;
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/* allocate memory for the internal state */
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state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
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if (state == NULL)
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goto error;
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ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
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if (ter_state == NULL)
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goto error;
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cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
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if (cab_state == NULL)
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goto error;
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/* setup the state */
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state->i2c = i2c;
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state->config = config;
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state->ter_state = ter_state;
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cab_state->search_range = 280000;
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cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
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state->cab_state = cab_state;
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state->fe.ops = stv0367ddb_ops;
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state->fe.demodulator_priv = state;
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state->chip_id = stv0367_readreg(state, R367TER_ID);
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/* demod operation options */
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state->use_i2c_gatectrl = 0;
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state->deftabs = STV0367_DEFTAB_DDB;
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state->reinit_on_setfrontend = 0;
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state->auto_if_khz = 1;
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state->activedemod = demod_none;
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dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
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/* check if the demod is there */
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if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
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goto error;
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dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
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state->fe.ops.info.name, state->chip_id,
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config->demod_address);
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stv0367ddb_init(state);
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return &state->fe;
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error:
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kfree(cab_state);
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kfree(ter_state);
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kfree(state);
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return NULL;
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}
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EXPORT_SYMBOL(stv0367ddb_attach);
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MODULE_PARM_DESC(debug, "Set debug");
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MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
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@ -44,6 +44,9 @@ dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
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extern struct
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dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
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struct i2c_adapter *i2c);
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extern struct
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dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
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struct i2c_adapter *i2c);
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#else
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static inline struct
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dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
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@ -59,6 +62,13 @@ dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
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printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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static inline struct
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dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
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struct i2c_adapter *i2c)
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{
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printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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#endif
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#endif
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