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V4L/DVB (7568): Support for DVB-S demod PN1010 (clone of S5H1420) added
This device is a clone of the PN1010 used by SkyStar2 rev2.7 . This patch adds support for the flexcop-device and makes the driver look a little bit nicer. It needs to be checked whether the driver is still ok for the budget-cards. Signed-off-by: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Patrick Boettcher
Mauro Carvalho Chehab
parent
44dc733cd9
commit
dbad108bdc
@ -1,23 +1,25 @@
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/*
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Driver for Samsung S5H1420 QPSK Demodulator
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Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* Driver for
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* Samsung S5H1420 and
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* PnpNetwork PN1010 QPSK Demodulator
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*
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* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
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* Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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@ -29,23 +31,35 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#include <linux/jiffies.h>
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#include <asm/div64.h>
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#include <linux/i2c.h>
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#include "dvb_frontend.h"
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#include "s5h1420.h"
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#include "s5h1420_priv.h"
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#define TONE_FREQ 22000
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struct s5h1420_state {
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struct i2c_adapter* i2c;
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const struct s5h1420_config* config;
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struct dvb_frontend frontend;
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struct i2c_adapter tuner_i2c_adapter;
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u8 CON_1_val;
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u8 postlocked:1;
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u32 fclk;
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u32 tunedfreq;
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fe_code_rate_t fec_inner;
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u32 symbol_rate;
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/* FIXME: ugly workaround for flexcop's incapable i2c-controller
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* it does not support repeated-start, workaround: write addr-1
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* and then read
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*/
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u8 shadow[255];
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};
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static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
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@ -54,7 +68,41 @@ static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
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static int debug;
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#define dprintk if (debug) printk
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "enable debugging");
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#define dprintk(x...) do { \
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if (debug) \
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printk(KERN_DEBUG "S5H1420: " x); \
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} while (0)
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static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
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{
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int ret;
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u8 b[2];
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struct i2c_msg msg[] = {
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{ .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
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{ .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
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{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
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};
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b[0] = (reg - 1) & 0xff;
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b[1] = state->shadow[(reg - 1) & 0xff];
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if (state->config->repeated_start_workaround) {
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ret = i2c_transfer(state->i2c, msg, 3);
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if (ret != 3)
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return ret;
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} else {
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ret = i2c_transfer(state->i2c, &msg[1], 2);
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if (ret != 2)
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return ret;
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}
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/* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
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return b[0];
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}
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static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
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{
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@ -62,35 +110,23 @@ static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
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struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
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int err;
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if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
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/* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
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err = i2c_transfer(state->i2c, &msg, 1);
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if (err != 1) {
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dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
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return -EREMOTEIO;
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}
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state->shadow[reg] = data;
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return 0;
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}
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static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
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{
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int ret;
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u8 b0 [] = { reg };
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u8 b1 [] = { 0 };
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struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
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struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
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if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
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return ret;
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if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
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return ret;
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return b1[0];
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}
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static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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dprintk("enter %s\n", __func__);
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switch(voltage) {
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case SEC_VOLTAGE_13:
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s5h1420_writereg(state, 0x3c,
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@ -106,6 +142,7 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
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break;
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}
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dprintk("leave %s\n", __func__);
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return 0;
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}
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@ -113,6 +150,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
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{
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struct s5h1420_state* state = fe->demodulator_priv;
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dprintk("enter %s\n", __func__);
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switch(tone) {
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case SEC_TONE_ON:
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s5h1420_writereg(state, 0x3b,
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@ -124,6 +162,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
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(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
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break;
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}
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dprintk("leave %s\n", __func__);
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return 0;
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}
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@ -137,6 +176,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
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unsigned long timeout;
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int result = 0;
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dprintk("enter %s\n", __func__);
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if (cmd->msg_len > 8)
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return -EINVAL;
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@ -168,6 +208,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
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/* restore original settings */
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s5h1420_writereg(state, 0x3b, val);
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msleep(15);
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dprintk("leave %s\n", __func__);
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return result;
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}
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@ -289,6 +330,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
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struct s5h1420_state* state = fe->demodulator_priv;
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u8 val;
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dprintk("enter %s\n", __func__);
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if (status == NULL)
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return -EINVAL;
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@ -298,12 +341,12 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
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/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
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the inversion, wait a bit and check again */
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if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
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val = s5h1420_readreg(state, 0x32);
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val = s5h1420_readreg(state, Vit10);
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if ((val & 0x07) == 0x03) {
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if (val & 0x08)
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s5h1420_writereg(state, 0x31, 0x13);
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s5h1420_writereg(state, Vit09, 0x13);
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else
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s5h1420_writereg(state, 0x31, 0x1b);
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s5h1420_writereg(state, Vit09, 0x1b);
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/* wait a bit then update lock status */
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mdelay(200);
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@ -312,68 +355,73 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
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}
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/* perform post lock setup */
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if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
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if ((*status & FE_HAS_LOCK) && !state->postlocked) {
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/* calculate the data rate */
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u32 tmp = s5h1420_getsymbolrate(state);
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switch(s5h1420_readreg(state, 0x32) & 0x07) {
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case 0:
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tmp = (tmp * 2 * 1) / 2;
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break;
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case 1:
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tmp = (tmp * 2 * 2) / 3;
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break;
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case 2:
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tmp = (tmp * 2 * 3) / 4;
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break;
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case 3:
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tmp = (tmp * 2 * 5) / 6;
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break;
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case 4:
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tmp = (tmp * 2 * 6) / 7;
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break;
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case 5:
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tmp = (tmp * 2 * 7) / 8;
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break;
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switch (s5h1420_readreg(state, Vit10) & 0x07) {
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case 0: tmp = (tmp * 2 * 1) / 2; break;
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case 1: tmp = (tmp * 2 * 2) / 3; break;
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case 2: tmp = (tmp * 2 * 3) / 4; break;
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case 3: tmp = (tmp * 2 * 5) / 6; break;
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case 4: tmp = (tmp * 2 * 6) / 7; break;
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case 5: tmp = (tmp * 2 * 7) / 8; break;
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}
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if (tmp == 0) {
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printk("s5h1420: avoided division by 0\n");
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printk(KERN_ERR "s5h1420: avoided division by 0\n");
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tmp = 1;
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}
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tmp = state->fclk / tmp;
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/* set the MPEG_CLK_INTL for the calculated data rate */
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if (tmp < 4)
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if (tmp < 2)
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val = 0x00;
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else if (tmp < 8)
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else if (tmp < 5)
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val = 0x01;
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else if (tmp < 12)
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else if (tmp < 9)
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val = 0x02;
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else if (tmp < 16)
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else if (tmp < 13)
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val = 0x03;
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else if (tmp < 24)
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else if (tmp < 17)
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val = 0x04;
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else if (tmp < 32)
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else if (tmp < 25)
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val = 0x05;
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else
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else if (tmp < 33)
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val = 0x06;
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s5h1420_writereg(state, 0x22, val);
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else
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val = 0x07;
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dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
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/* DC freeze */
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s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
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s5h1420_writereg(state, FEC01, 0x18);
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s5h1420_writereg(state, FEC01, 0x10);
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s5h1420_writereg(state, FEC01, val);
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/* kicker disable + remove DC offset */
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s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
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/* Enable "MPEG_Out" */
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val = s5h1420_readreg(state, Mpeg02);
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s5h1420_writereg(state, Mpeg02, val | (1 << 6));
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/* kicker disable */
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val = s5h1420_readreg(state, QPSK01) & 0x7f;
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s5h1420_writereg(state, QPSK01, val);
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/* DC freeze TODO it was never activated by default or it can stay activated */
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if (s5h1420_getsymbolrate(state) >= 20000000) {
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s5h1420_writereg(state, Loop04, 0x8a);
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s5h1420_writereg(state, Loop05, 0x6a);
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} else {
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s5h1420_writereg(state, Loop04, 0x58);
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s5h1420_writereg(state, Loop05, 0x27);
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}
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/* post-lock processing has been done! */
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state->postlocked = 1;
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}
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dprintk("leave %s\n", __func__);
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return 0;
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}
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@ -414,6 +462,7 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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static void s5h1420_reset(struct s5h1420_state* state)
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{
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dprintk("%s\n", __func__);
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s5h1420_writereg (state, 0x01, 0x08);
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s5h1420_writereg (state, 0x01, 0x00);
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udelay(10);
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@ -422,54 +471,52 @@ static void s5h1420_reset(struct s5h1420_state* state)
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static void s5h1420_setsymbolrate(struct s5h1420_state* state,
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struct dvb_frontend_parameters *p)
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{
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u8 v;
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u64 val;
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dprintk("enter %s\n", __func__);
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val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
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if (p->u.qpsk.symbol_rate <= 21000000) {
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if (p->u.qpsk.symbol_rate < 29000000)
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val *= 2;
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}
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do_div(val, (state->fclk / 1000));
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s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
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s5h1420_writereg(state, 0x11, val >> 16);
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s5h1420_writereg(state, 0x12, val >> 8);
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s5h1420_writereg(state, 0x13, val & 0xff);
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s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
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dprintk("symbol rate register: %06llx\n", val);
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v = s5h1420_readreg(state, Loop01);
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s5h1420_writereg(state, Loop01, v & 0x7f);
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s5h1420_writereg(state, Tnco01, val >> 16);
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s5h1420_writereg(state, Tnco02, val >> 8);
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s5h1420_writereg(state, Tnco03, val & 0xff);
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s5h1420_writereg(state, Loop01, v | 0x80);
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dprintk("leave %s\n", __func__);
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}
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static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
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{
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u64 val = 0;
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int sampling = 2;
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if (s5h1420_readreg(state, 0x05) & 0x2)
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sampling = 1;
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s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
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val = s5h1420_readreg(state, 0x11) << 16;
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val |= s5h1420_readreg(state, 0x12) << 8;
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val |= s5h1420_readreg(state, 0x13);
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s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
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val *= (state->fclk / 1000ULL);
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do_div(val, ((1<<24) * sampling));
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return (u32) (val * 1000ULL);
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return state->symbol_rate;
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}
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static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
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{
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int val;
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u8 v;
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dprintk("enter %s\n", __func__);
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/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
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* divide fclk by 1000000 to get the correct value. */
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val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
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s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
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s5h1420_writereg(state, 0x0e, val >> 16);
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s5h1420_writereg(state, 0x0f, val >> 8);
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s5h1420_writereg(state, 0x10, val & 0xff);
|
||||
s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
|
||||
dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
|
||||
|
||||
v = s5h1420_readreg(state, Loop01);
|
||||
s5h1420_writereg(state, Loop01, v & 0xbf);
|
||||
s5h1420_writereg(state, Pnco01, val >> 16);
|
||||
s5h1420_writereg(state, Pnco02, val >> 8);
|
||||
s5h1420_writereg(state, Pnco03, val & 0xff);
|
||||
s5h1420_writereg(state, Loop01, v | 0x40);
|
||||
dprintk("leave %s\n", __func__);
|
||||
}
|
||||
|
||||
static int s5h1420_getfreqoffset(struct s5h1420_state* state)
|
||||
@ -496,52 +543,53 @@ static void s5h1420_setfec_inversion(struct s5h1420_state* state,
|
||||
struct dvb_frontend_parameters *p)
|
||||
{
|
||||
u8 inversion = 0;
|
||||
u8 vit08, vit09;
|
||||
|
||||
if (p->inversion == INVERSION_OFF) {
|
||||
dprintk("enter %s\n", __func__);
|
||||
|
||||
if (p->inversion == INVERSION_OFF)
|
||||
inversion = state->config->invert ? 0x08 : 0;
|
||||
} else if (p->inversion == INVERSION_ON) {
|
||||
else if (p->inversion == INVERSION_ON)
|
||||
inversion = state->config->invert ? 0 : 0x08;
|
||||
}
|
||||
|
||||
if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
|
||||
s5h1420_writereg(state, 0x30, 0x3f);
|
||||
s5h1420_writereg(state, 0x31, 0x00 | inversion);
|
||||
vit08 = 0x3f;
|
||||
vit09 = 0;
|
||||
} else {
|
||||
switch(p->u.qpsk.fec_inner) {
|
||||
case FEC_1_2:
|
||||
s5h1420_writereg(state, 0x30, 0x01);
|
||||
s5h1420_writereg(state, 0x31, 0x10 | inversion);
|
||||
vit08 = 0x01; vit09 = 0x10;
|
||||
break;
|
||||
|
||||
case FEC_2_3:
|
||||
s5h1420_writereg(state, 0x30, 0x02);
|
||||
s5h1420_writereg(state, 0x31, 0x11 | inversion);
|
||||
vit08 = 0x02; vit09 = 0x11;
|
||||
break;
|
||||
|
||||
case FEC_3_4:
|
||||
s5h1420_writereg(state, 0x30, 0x04);
|
||||
s5h1420_writereg(state, 0x31, 0x12 | inversion);
|
||||
vit08 = 0x04; vit09 = 0x12;
|
||||
break;
|
||||
|
||||
case FEC_5_6:
|
||||
s5h1420_writereg(state, 0x30, 0x08);
|
||||
s5h1420_writereg(state, 0x31, 0x13 | inversion);
|
||||
vit08 = 0x08; vit09 = 0x13;
|
||||
break;
|
||||
|
||||
case FEC_6_7:
|
||||
s5h1420_writereg(state, 0x30, 0x10);
|
||||
s5h1420_writereg(state, 0x31, 0x14 | inversion);
|
||||
vit08 = 0x10; vit09 = 0x14;
|
||||
break;
|
||||
|
||||
case FEC_7_8:
|
||||
s5h1420_writereg(state, 0x30, 0x20);
|
||||
s5h1420_writereg(state, 0x31, 0x15 | inversion);
|
||||
vit08 = 0x20; vit09 = 0x15;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
vit09 |= inversion;
|
||||
dprintk("fec: %02x %02x\n", vit08, vit09);
|
||||
s5h1420_writereg(state, Vit08, vit08);
|
||||
s5h1420_writereg(state, Vit09, vit09);
|
||||
dprintk("leave %s\n", __func__);
|
||||
}
|
||||
|
||||
static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
|
||||
@ -583,6 +631,9 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
int frequency_delta;
|
||||
struct dvb_frontend_tune_settings fesettings;
|
||||
uint8_t clock_settting;
|
||||
|
||||
dprintk("enter %s\n", __func__);
|
||||
|
||||
/* check if we should do a fast-tune */
|
||||
memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
|
||||
@ -606,54 +657,93 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
|
||||
} else {
|
||||
s5h1420_setfreqoffset(state, 0);
|
||||
}
|
||||
dprintk("simple tune\n");
|
||||
return 0;
|
||||
}
|
||||
dprintk("tuning demod\n");
|
||||
|
||||
/* first of all, software reset */
|
||||
s5h1420_reset(state);
|
||||
|
||||
/* set s5h1420 fclk PLL according to desired symbol rate */
|
||||
if (p->u.qpsk.symbol_rate > 28000000) {
|
||||
state->fclk = 88000000;
|
||||
s5h1420_writereg(state, 0x03, 0x50);
|
||||
s5h1420_writereg(state, 0x04, 0x40);
|
||||
s5h1420_writereg(state, 0x05, 0xae);
|
||||
} else if (p->u.qpsk.symbol_rate > 21000000) {
|
||||
if (p->u.qpsk.symbol_rate > 33000000)
|
||||
state->fclk = 80000000;
|
||||
else if (p->u.qpsk.symbol_rate > 28500000)
|
||||
state->fclk = 59000000;
|
||||
s5h1420_writereg(state, 0x03, 0x33);
|
||||
s5h1420_writereg(state, 0x04, 0x40);
|
||||
s5h1420_writereg(state, 0x05, 0xae);
|
||||
} else {
|
||||
else if (p->u.qpsk.symbol_rate > 25000000)
|
||||
state->fclk = 86000000;
|
||||
else if (p->u.qpsk.symbol_rate > 1900000)
|
||||
state->fclk = 88000000;
|
||||
s5h1420_writereg(state, 0x03, 0x50);
|
||||
s5h1420_writereg(state, 0x04, 0x40);
|
||||
s5h1420_writereg(state, 0x05, 0xac);
|
||||
else
|
||||
state->fclk = 44000000;
|
||||
|
||||
/* Clock */
|
||||
switch (state->fclk) {
|
||||
default:
|
||||
case 88000000:
|
||||
clock_settting = 80;
|
||||
break;
|
||||
case 86000000:
|
||||
clock_settting = 78;
|
||||
break;
|
||||
case 80000000:
|
||||
clock_settting = 72;
|
||||
break;
|
||||
case 59000000:
|
||||
clock_settting = 51;
|
||||
break;
|
||||
case 44000000:
|
||||
clock_settting = 36;
|
||||
break;
|
||||
}
|
||||
dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
|
||||
s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
|
||||
s5h1420_writereg(state, PLL02, 0x40);
|
||||
s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
|
||||
|
||||
/* TODO DC offset removal, config parameter ? */
|
||||
if (p->u.qpsk.symbol_rate > 29000000)
|
||||
s5h1420_writereg(state, QPSK01, 0xae | 0x10);
|
||||
else
|
||||
s5h1420_writereg(state, QPSK01, 0xac | 0x10);
|
||||
|
||||
/* set misc registers */
|
||||
s5h1420_writereg(state, 0x02, 0x00);
|
||||
s5h1420_writereg(state, 0x06, 0x00);
|
||||
s5h1420_writereg(state, 0x07, 0xb0);
|
||||
s5h1420_writereg(state, 0x0a, 0xe7);
|
||||
s5h1420_writereg(state, 0x0b, 0x78);
|
||||
s5h1420_writereg(state, 0x0c, 0x48);
|
||||
s5h1420_writereg(state, 0x0d, 0x6b);
|
||||
s5h1420_writereg(state, 0x2e, 0x8e);
|
||||
s5h1420_writereg(state, 0x35, 0x33);
|
||||
s5h1420_writereg(state, 0x38, 0x01);
|
||||
s5h1420_writereg(state, 0x39, 0x7d);
|
||||
s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
|
||||
s5h1420_writereg(state, 0x3c, 0x00);
|
||||
s5h1420_writereg(state, 0x45, 0x61);
|
||||
s5h1420_writereg(state, 0x46, 0x1d);
|
||||
s5h1420_writereg(state, CON_1, 0x00);
|
||||
s5h1420_writereg(state, QPSK02, 0x00);
|
||||
s5h1420_writereg(state, Pre01, 0xb0);
|
||||
|
||||
/* start QPSK */
|
||||
s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
|
||||
s5h1420_writereg(state, Loop01, 0xF0);
|
||||
s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
|
||||
s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
|
||||
if (p->u.qpsk.symbol_rate > 20000000)
|
||||
s5h1420_writereg(state, Loop04, 0x79);
|
||||
else
|
||||
s5h1420_writereg(state, Loop04, 0x58);
|
||||
s5h1420_writereg(state, Loop05, 0x6b);
|
||||
|
||||
if (p->u.qpsk.symbol_rate >= 8000000)
|
||||
s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
|
||||
else if (p->u.qpsk.symbol_rate >= 4000000)
|
||||
s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
|
||||
else
|
||||
s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
|
||||
|
||||
s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
|
||||
|
||||
s5h1420_writereg(state, Sync01, 0x33);
|
||||
s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
|
||||
s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
|
||||
s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
|
||||
|
||||
s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
|
||||
s5h1420_writereg(state, DiS03, 0x00);
|
||||
s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
|
||||
|
||||
/* set tuner PLL */
|
||||
if (fe->ops.tuner_ops.set_params) {
|
||||
fe->ops.tuner_ops.set_params(fe, p);
|
||||
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 0);
|
||||
s5h1420_setfreqoffset(state, 0);
|
||||
}
|
||||
|
||||
@ -661,10 +751,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
|
||||
s5h1420_setsymbolrate(state, p);
|
||||
s5h1420_setfec_inversion(state, p);
|
||||
|
||||
/* start QPSK */
|
||||
s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
|
||||
|
||||
state->fec_inner = p->u.qpsk.fec_inner;
|
||||
state->symbol_rate = p->u.qpsk.symbol_rate;
|
||||
state->postlocked = 0;
|
||||
state->tunedfreq = p->frequency;
|
||||
|
||||
dprintk("leave %s\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -717,11 +812,10 @@ static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
|
||||
{
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
|
||||
if (enable) {
|
||||
return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
|
||||
} else {
|
||||
return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
|
||||
}
|
||||
if (enable)
|
||||
return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
|
||||
else
|
||||
return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
|
||||
}
|
||||
|
||||
static int s5h1420_init (struct dvb_frontend* fe)
|
||||
@ -729,7 +823,8 @@ static int s5h1420_init (struct dvb_frontend* fe)
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
|
||||
/* disable power down and do reset */
|
||||
s5h1420_writereg(state, 0x02, 0x10);
|
||||
state->CON_1_val = 0x10;
|
||||
s5h1420_writereg(state, 0x02, state->CON_1_val);
|
||||
msleep(10);
|
||||
s5h1420_reset(state);
|
||||
|
||||
@ -739,26 +834,60 @@ static int s5h1420_init (struct dvb_frontend* fe)
|
||||
static int s5h1420_sleep(struct dvb_frontend* fe)
|
||||
{
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
|
||||
return s5h1420_writereg(state, 0x02, 0x12);
|
||||
state->CON_1_val = 0x12;
|
||||
return s5h1420_writereg(state, 0x02, state->CON_1_val);
|
||||
}
|
||||
|
||||
static void s5h1420_release(struct dvb_frontend* fe)
|
||||
{
|
||||
struct s5h1420_state* state = fe->demodulator_priv;
|
||||
i2c_del_adapter(&state->tuner_i2c_adapter);
|
||||
kfree(state);
|
||||
}
|
||||
|
||||
static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C;
|
||||
}
|
||||
|
||||
static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
|
||||
{
|
||||
struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
|
||||
struct i2c_msg m[1 + num];
|
||||
u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
|
||||
|
||||
memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
|
||||
|
||||
m[0].addr = state->config->demod_address;
|
||||
m[0].buf = tx_open;
|
||||
m[0].len = 2;
|
||||
|
||||
memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
|
||||
|
||||
return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
|
||||
.master_xfer = s5h1420_tuner_i2c_tuner_xfer,
|
||||
.functionality = s5h1420_tuner_i2c_func,
|
||||
};
|
||||
|
||||
struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
|
||||
{
|
||||
struct s5h1420_state *state = fe->demodulator_priv;
|
||||
return &state->tuner_i2c_adapter;
|
||||
}
|
||||
EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
|
||||
|
||||
static struct dvb_frontend_ops s5h1420_ops;
|
||||
|
||||
struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
|
||||
struct i2c_adapter *i2c)
|
||||
{
|
||||
struct s5h1420_state* state = NULL;
|
||||
u8 identity;
|
||||
|
||||
/* allocate memory for the internal state */
|
||||
state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
|
||||
struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
|
||||
u8 i;
|
||||
|
||||
if (state == NULL)
|
||||
goto error;
|
||||
|
||||
@ -772,24 +901,42 @@ struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
|
||||
state->symbol_rate = 0;
|
||||
|
||||
/* check if the demod is there + identify it */
|
||||
identity = s5h1420_readreg(state, 0x00);
|
||||
if (identity != 0x03)
|
||||
i = s5h1420_readreg(state, ID01);
|
||||
if (i != 0x03)
|
||||
goto error;
|
||||
|
||||
memset(state->shadow, 0xff, sizeof(state->shadow));
|
||||
|
||||
for (i = 0; i < 0x50; i++)
|
||||
state->shadow[i] = s5h1420_readreg(state, i);
|
||||
|
||||
/* create dvb_frontend */
|
||||
memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
|
||||
state->frontend.demodulator_priv = state;
|
||||
|
||||
/* create tuner i2c adapter */
|
||||
strncpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", I2C_NAME_SIZE);
|
||||
state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL,
|
||||
state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
|
||||
state->tuner_i2c_adapter.algo_data = NULL;
|
||||
i2c_set_adapdata(&state->tuner_i2c_adapter, state);
|
||||
if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
|
||||
printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
return &state->frontend;
|
||||
|
||||
error:
|
||||
kfree(state);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(s5h1420_attach);
|
||||
|
||||
static struct dvb_frontend_ops s5h1420_ops = {
|
||||
|
||||
.info = {
|
||||
.name = "Samsung S5H1420 DVB-S",
|
||||
.name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
|
||||
.type = FE_QPSK,
|
||||
.frequency_min = 950000,
|
||||
.frequency_max = 2150000,
|
||||
@ -826,10 +973,6 @@ static struct dvb_frontend_ops s5h1420_ops = {
|
||||
.set_voltage = s5h1420_set_voltage,
|
||||
};
|
||||
|
||||
module_param(debug, int, 0644);
|
||||
|
||||
MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
|
||||
MODULE_AUTHOR("Andrew de Quincey");
|
||||
MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
|
||||
MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
EXPORT_SYMBOL(s5h1420_attach);
|
||||
|
||||
@ -1,25 +1,26 @@
|
||||
/*
|
||||
Driver for S5H1420 QPSK Demodulators
|
||||
|
||||
Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
* Driver for
|
||||
* Samsung S5H1420 and
|
||||
* PnpNetwork PN1010 QPSK Demodulator
|
||||
*
|
||||
* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
|
||||
* Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef S5H1420_H
|
||||
#define S5H1420_H
|
||||
|
||||
@ -32,11 +33,15 @@ struct s5h1420_config
|
||||
|
||||
/* does the inversion require inversion? */
|
||||
u8 invert : 1;
|
||||
|
||||
u8 repeated_start_workaround : 1;
|
||||
u8 cdclk_polarity : 1; /* 1 == falling edge, 0 == raising edge */
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DVB_S5H1420) || (defined(CONFIG_DVB_S5H1420_MODULE) && defined(MODULE))
|
||||
extern struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
|
||||
struct i2c_adapter *i2c);
|
||||
extern struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe);
|
||||
#else
|
||||
static inline struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
|
||||
struct i2c_adapter *i2c)
|
||||
@ -44,6 +49,11 @@ static inline struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* c
|
||||
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif // CONFIG_DVB_S5H1420
|
||||
|
||||
#endif // S5H1420_H
|
||||
|
||||
102
drivers/media/dvb/frontends/s5h1420_priv.h
Normal file
102
drivers/media/dvb/frontends/s5h1420_priv.h
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Driver for
|
||||
* Samsung S5H1420 and
|
||||
* PnpNetwork PN1010 QPSK Demodulator
|
||||
*
|
||||
* Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
|
||||
* Copyright (C) 2005 Patrick Boettcher <pb@linuxtv.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 675 Mass
|
||||
* Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef S5H1420_PRIV
|
||||
#define S5H1420_PRIV
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
enum s5h1420_register {
|
||||
ID01 = 0x00,
|
||||
CON_0 = 0x01,
|
||||
CON_1 = 0x02,
|
||||
PLL01 = 0x03,
|
||||
PLL02 = 0x04,
|
||||
QPSK01 = 0x05,
|
||||
QPSK02 = 0x06,
|
||||
Pre01 = 0x07,
|
||||
Post01 = 0x08,
|
||||
Loop01 = 0x09,
|
||||
Loop02 = 0x0a,
|
||||
Loop03 = 0x0b,
|
||||
Loop04 = 0x0c,
|
||||
Loop05 = 0x0d,
|
||||
Pnco01 = 0x0e,
|
||||
Pnco02 = 0x0f,
|
||||
Pnco03 = 0x10,
|
||||
Tnco01 = 0x11,
|
||||
Tnco02 = 0x12,
|
||||
Tnco03 = 0x13,
|
||||
Monitor01 = 0x14,
|
||||
Monitor02 = 0x15,
|
||||
Monitor03 = 0x16,
|
||||
Monitor04 = 0x17,
|
||||
Monitor05 = 0x18,
|
||||
Monitor06 = 0x19,
|
||||
Monitor07 = 0x1a,
|
||||
Monitor12 = 0x1f,
|
||||
|
||||
FEC01 = 0x22,
|
||||
Soft01 = 0x23,
|
||||
Soft02 = 0x24,
|
||||
Soft03 = 0x25,
|
||||
Soft04 = 0x26,
|
||||
Soft05 = 0x27,
|
||||
Soft06 = 0x28,
|
||||
Vit01 = 0x29,
|
||||
Vit02 = 0x2a,
|
||||
Vit03 = 0x2b,
|
||||
Vit04 = 0x2c,
|
||||
Vit05 = 0x2d,
|
||||
Vit06 = 0x2e,
|
||||
Vit07 = 0x2f,
|
||||
Vit08 = 0x30,
|
||||
Vit09 = 0x31,
|
||||
Vit10 = 0x32,
|
||||
Vit11 = 0x33,
|
||||
Vit12 = 0x34,
|
||||
Sync01 = 0x35,
|
||||
Sync02 = 0x36,
|
||||
Rs01 = 0x37,
|
||||
Mpeg01 = 0x38,
|
||||
Mpeg02 = 0x39,
|
||||
DiS01 = 0x3a,
|
||||
DiS02 = 0x3b,
|
||||
DiS03 = 0x3c,
|
||||
DiS04 = 0x3d,
|
||||
DiS05 = 0x3e,
|
||||
DiS06 = 0x3f,
|
||||
DiS07 = 0x40,
|
||||
DiS08 = 0x41,
|
||||
DiS09 = 0x42,
|
||||
DiS10 = 0x43,
|
||||
DiS11 = 0x44,
|
||||
Rf01 = 0x45,
|
||||
Err01 = 0x46,
|
||||
Err02 = 0x47,
|
||||
Err03 = 0x48,
|
||||
Err04 = 0x49,
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
@ -358,6 +358,7 @@ static int s5h1420_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend
|
||||
static struct s5h1420_config s5h1420_config = {
|
||||
.demod_address = 0x53,
|
||||
.invert = 1,
|
||||
.cdclk_polarity = 1,
|
||||
};
|
||||
|
||||
static struct tda10086_config tda10086_config = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user