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clk: qcom: gcc-sdm660: Replace usage of parent_names
Using parent_data and parent_hws, instead of parent_names, does protect against some cases of incompletely defined clock trees. While it turns out that the bug being chased this time was totally unrelated, this patch converts the SDM660 GCC driver to avoid such issues. The "xo" fixed_factor clock is unused within the gcc driver, but referenced from the DSI PHY. So it's left in place until the DSI driver is updated. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org [sboyd@kernel.org: Reduce diff by moving enum and tables back to original position in previous patch] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Bjorn Andersson
Stephen Boyd
parent
a61ca021fe
commit
da09577ab5
@ -42,7 +42,9 @@ static struct clk_fixed_factor xo = {
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.div = 1,
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.hw.init = &(struct clk_init_data){
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.name = "xo",
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.parent_names = (const char *[]){ "xo_board" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xo"
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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},
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@ -56,7 +58,9 @@ static struct clk_alpha_pll gpll0_early = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpll0_early",
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.parent_names = (const char *[]){ "xo" },
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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@ -68,7 +72,9 @@ static struct clk_fixed_factor gpll0_early_div = {
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "gpll0_early_div",
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.parent_names = (const char *[]){ "gpll0_early" },
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.parent_hws = (const struct clk_hw*[]){
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&gpll0_early.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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},
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@ -79,7 +85,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0",
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.parent_names = (const char *[]){ "gpll0_early" },
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.parent_hws = (const struct clk_hw*[]){
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&gpll0_early.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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@ -93,7 +101,9 @@ static struct clk_alpha_pll gpll1_early = {
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gpll1_early",
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.parent_names = (const char *[]){ "xo" },
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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@ -105,7 +115,9 @@ static struct clk_fixed_factor gpll1_early_div = {
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "gpll1_early_div",
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.parent_names = (const char *[]){ "gpll1_early" },
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.parent_hws = (const struct clk_hw*[]){
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&gpll1_early.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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},
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@ -116,7 +128,9 @@ static struct clk_alpha_pll_postdiv gpll1 = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll1",
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.parent_names = (const char *[]){ "gpll1_early" },
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.parent_hws = (const struct clk_hw*[]){
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&gpll1_early.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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@ -130,7 +144,9 @@ static struct clk_alpha_pll gpll4_early = {
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "gpll4_early",
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.parent_names = (const char *[]){ "xo" },
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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@ -143,7 +159,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
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.clkr.hw.init = &(struct clk_init_data)
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{
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.name = "gpll4",
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.parent_names = (const char *[]) { "gpll4_early" },
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.parent_hws = (const struct clk_hw*[]){
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&gpll4_early.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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@ -155,10 +173,10 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
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{ P_GPLL0_EARLY_DIV, 6 },
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};
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static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
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"xo",
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"gpll0",
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"gpll0_early_div",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll0_early_div.hw },
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};
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static const struct parent_map gcc_parent_map_xo_gpll0[] = {
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@ -166,9 +184,9 @@ static const struct parent_map gcc_parent_map_xo_gpll0[] = {
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{ P_GPLL0, 1 },
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};
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static const char * const gcc_parent_names_xo_gpll0[] = {
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"xo",
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"gpll0",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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};
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static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
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@ -178,11 +196,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div
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{ P_GPLL0_EARLY_DIV, 6 },
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};
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static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
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"xo",
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"gpll0",
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"sleep_clk",
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"gpll0_early_div",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .fw_name = "sleep_clk" },
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{ .hw = &gpll0_early_div.hw },
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};
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static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
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@ -190,9 +208,9 @@ static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
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{ P_SLEEP_CLK, 5 },
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};
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static const char * const gcc_parent_names_xo_sleep_clk[] = {
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"xo",
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"sleep_clk",
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static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = {
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{ .fw_name = "xo" },
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{ .fw_name = "sleep_clk" },
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};
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static const struct parent_map gcc_parent_map_xo_gpll4[] = {
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@ -200,9 +218,9 @@ static const struct parent_map gcc_parent_map_xo_gpll4[] = {
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{ P_GPLL4, 5 },
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};
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static const char * const gcc_parent_names_xo_gpll4[] = {
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"xo",
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"gpll4",
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static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll4.clkr.hw },
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};
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static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
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@ -214,13 +232,13 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpl
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{ P_GPLL1_EARLY_DIV, 6 },
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};
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static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
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"xo",
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"gpll0",
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"gpll0_early_div",
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"gpll1",
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"gpll4",
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"gpll1_early_div",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll0_early_div.hw },
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{ .hw = &gpll1.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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{ .hw = &gpll1_early_div.hw },
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};
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static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
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@ -230,11 +248,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] =
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{ P_GPLL0_EARLY_DIV, 6 },
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};
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static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
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"xo",
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"gpll0",
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"gpll4",
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"gpll0_early_div",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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{ .hw = &gpll0_early_div.hw },
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};
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static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
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@ -244,11 +262,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] =
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{ P_GPLL4, 5 },
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};
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static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
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"xo",
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"gpll0",
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"gpll0_early_div",
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"gpll4",
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static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll0_early_div.hw },
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{ .hw = &gpll4.clkr.hw },
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};
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static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
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@ -265,7 +283,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup1_i2c_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -290,7 +308,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup1_spi_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -304,7 +322,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup2_i2c_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -318,7 +336,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup2_spi_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -332,7 +350,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup3_i2c_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -346,7 +364,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup3_spi_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -360,7 +378,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup4_i2c_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -374,7 +392,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup4_spi_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -407,7 +425,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_uart1_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -421,7 +439,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_uart2_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -435,7 +453,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp2_qup1_i2c_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -449,7 +467,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp2_qup1_spi_apps_clk_src",
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.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
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.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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@ -463,7 +481,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup2_i2c_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -477,7 +495,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup2_spi_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -491,7 +509,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup3_i2c_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -505,7 +523,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup3_spi_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -519,7 +537,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup4_i2c_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -533,7 +551,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_qup4_spi_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -547,7 +565,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_uart1_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -561,7 +579,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
|
||||
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "blsp2_uart2_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -582,7 +600,7 @@ static struct clk_rcg2 gp1_clk_src = {
|
||||
.freq_tbl = ftbl_gp1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gp1_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -596,7 +614,7 @@ static struct clk_rcg2 gp2_clk_src = {
|
||||
.freq_tbl = ftbl_gp1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gp2_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -610,7 +628,7 @@ static struct clk_rcg2 gp3_clk_src = {
|
||||
.freq_tbl = ftbl_gp1_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gp3_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -630,7 +648,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
|
||||
.freq_tbl = ftbl_hmss_gpll0_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "hmss_gpll0_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -651,7 +669,7 @@ static struct clk_rcg2 hmss_gpll4_clk_src = {
|
||||
.freq_tbl = ftbl_hmss_gpll4_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "hmss_gpll4_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll4,
|
||||
.parent_data = gcc_parent_data_xo_gpll4,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -670,7 +688,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
|
||||
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "hmss_rbcpr_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0,
|
||||
.parent_data = gcc_parent_data_xo_gpll0,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -689,7 +707,7 @@ static struct clk_rcg2 pdm2_clk_src = {
|
||||
.freq_tbl = ftbl_pdm2_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "pdm2_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -711,7 +729,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
|
||||
.freq_tbl = ftbl_qspi_ser_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "qspi_ser_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
|
||||
.num_parents = 6,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -737,7 +755,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
||||
.freq_tbl = ftbl_sdcc1_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "sdcc1_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -759,7 +777,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
|
||||
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "sdcc1_ice_core_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -785,7 +803,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
|
||||
.freq_tbl = ftbl_sdcc2_apps_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "sdcc2_apps_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
@ -808,7 +826,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
|
||||
.freq_tbl = ftbl_ufs_axi_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "ufs_axi_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -829,7 +847,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
|
||||
.freq_tbl = ftbl_ufs_ice_core_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "ufs_ice_core_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -843,7 +861,7 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = {
|
||||
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "ufs_phy_aux_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_sleep_clk,
|
||||
.parent_data = gcc_parent_data_xo_sleep_clk,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -864,7 +882,7 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = {
|
||||
.freq_tbl = ftbl_ufs_unipro_core_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "ufs_unipro_core_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -885,7 +903,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
|
||||
.freq_tbl = ftbl_usb20_master_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "usb20_master_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -905,7 +923,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
|
||||
.freq_tbl = ftbl_usb20_mock_utmi_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "usb20_mock_utmi_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -930,7 +948,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
|
||||
.freq_tbl = ftbl_usb30_master_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "usb30_master_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -951,7 +969,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
|
||||
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "usb30_mock_utmi_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
|
||||
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
|
||||
.num_parents = 3,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -971,7 +989,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
|
||||
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "usb3_phy_aux_clk_src",
|
||||
.parent_names = gcc_parent_names_xo_sleep_clk,
|
||||
.parent_data = gcc_parent_data_xo_sleep_clk,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
@ -985,8 +1003,8 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_aggre2_ufs_axi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"ufs_axi_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&ufs_axi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1002,8 +1020,8 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_aggre2_usb3_axi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb30_master_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb30_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1071,8 +1089,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup1_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup1_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1089,8 +1107,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup1_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup1_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1107,8 +1125,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup2_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup2_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1125,8 +1143,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup2_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup2_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1143,8 +1161,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup3_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup3_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1161,8 +1179,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup3_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup3_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1179,8 +1197,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup4_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup4_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1197,8 +1215,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_qup4_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_qup4_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1215,8 +1233,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_uart1_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_uart1_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_uart1_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1233,8 +1251,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp1_uart2_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp1_uart2_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp1_uart2_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1264,8 +1282,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup1_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup1_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1282,8 +1300,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup1_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup1_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1300,8 +1318,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup2_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup2_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1318,8 +1336,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup2_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup2_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1336,8 +1354,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup3_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup3_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1354,8 +1372,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup3_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup3_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1372,8 +1390,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup4_i2c_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup4_i2c_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1390,8 +1408,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_qup4_spi_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_qup4_spi_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1408,8 +1426,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_uart1_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_uart1_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_uart1_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1426,8 +1444,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_blsp2_uart2_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"blsp2_uart2_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&blsp2_uart2_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1457,8 +1475,8 @@ static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_cfg_noc_usb2_axi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb20_master_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb20_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1474,8 +1492,8 @@ static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_cfg_noc_usb3_axi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb30_master_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb30_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1503,8 +1521,8 @@ static struct clk_branch gcc_gp1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gp1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gp1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1521,8 +1539,8 @@ static struct clk_branch gcc_gp2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp2_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gp2_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gp2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1539,8 +1557,8 @@ static struct clk_branch gcc_gp3_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp3_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gp3_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gp3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1584,8 +1602,8 @@ static struct clk_branch gcc_gpu_gpll0_clk = {
|
||||
.enable_mask = BIT(4),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gpu_gpll0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gpll0",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpll0.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1601,8 +1619,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = {
|
||||
.enable_mask = BIT(3),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gpu_gpll0_div_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gpll0_early_div",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpll0_early_div.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1632,8 +1650,8 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_hmss_rbcpr_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"hmss_rbcpr_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&hmss_rbcpr_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1650,8 +1668,8 @@ static struct clk_branch gcc_mmss_gpll0_clk = {
|
||||
.enable_mask = BIT(1),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mmss_gpll0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gpll0",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpll0.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1667,8 +1685,8 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mmss_gpll0_div_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"gpll0_early_div",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpll0_early_div.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -1767,8 +1785,8 @@ static struct clk_branch gcc_pdm2_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pdm2_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"pdm2_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&pdm2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1824,8 +1842,8 @@ static struct clk_branch gcc_qspi_ser_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qspi_ser_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"qspi_ser_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&qspi_ser_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1881,8 +1899,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc1_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"sdcc1_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&sdcc1_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1899,8 +1917,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc1_ice_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"sdcc1_ice_core_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&sdcc1_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1930,8 +1948,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc2_apps_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"sdcc2_apps_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&sdcc2_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1961,8 +1979,8 @@ static struct clk_branch gcc_ufs_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_axi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"ufs_axi_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&ufs_axi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1992,8 +2010,8 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_ice_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"ufs_ice_core_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&ufs_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2010,8 +2028,8 @@ static struct clk_branch gcc_ufs_phy_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_aux_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"ufs_phy_aux_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&ufs_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2067,8 +2085,8 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_unipro_core_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"ufs_unipro_core_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&ufs_unipro_core_clk_src.clkr.hw,
|
||||
},
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.num_parents = 1,
|
||||
@ -2085,8 +2103,8 @@ static struct clk_branch gcc_usb20_master_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb20_master_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb20_master_clk_src"
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb20_master_clk_src.clkr.hw,
|
||||
},
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.num_parents = 1,
|
||||
@ -2103,8 +2121,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb20_mock_utmi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb20_mock_utmi_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb20_mock_utmi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2134,8 +2152,8 @@ static struct clk_branch gcc_usb30_master_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_master_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb30_master_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb30_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2152,8 +2170,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_mock_utmi_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb30_mock_utmi_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb30_mock_utmi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2196,8 +2214,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_phy_aux_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"usb3_phy_aux_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&usb3_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user