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ARM: LPAE: Page table maintenance for the 3-level format
This patch modifies the pgd/pmd/pte manipulation functions to support the 3-level page table format. Since there is no need for an 'ext' argument to cpu_set_pte_ext(), this patch conditionally defines a different prototype for this function when CONFIG_ARM_LPAE. The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid trying to free them at run-time. This flag is 0 with the classic page table format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas
parent
dcfdae04bd
commit
da02877987
@ -25,6 +25,26 @@
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#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
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#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
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#ifdef CONFIG_ARM_LPAE
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static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
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}
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static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
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{
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BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
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free_page((unsigned long)pmd);
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}
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static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
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{
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set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
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}
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#else /* !CONFIG_ARM_LPAE */
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/*
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* Since we have only two-level page tables, these are trivial
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*/
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@ -32,6 +52,8 @@
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#define pmd_free(mm, pmd) do { } while (0)
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#define pud_populate(mm,pmd,pte) BUG()
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#endif /* CONFIG_ARM_LPAE */
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
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@ -109,7 +131,9 @@ static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
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{
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pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot;
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pmdp[0] = __pmd(pmdval);
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#ifndef CONFIG_ARM_LPAE
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pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
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#endif
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flush_pmd_entry(pmdp);
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}
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@ -99,4 +99,57 @@
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#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
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/*
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* Software PGD flags.
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*/
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#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
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#ifndef __ASSEMBLY__
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (!(pud_val(pud) & 2))
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#define pud_present(pud) (pud_val(pud))
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#define pud_clear(pudp) \
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do { \
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*pudp = __pud(0); \
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clean_pmd_entry(pudp); \
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} while (0)
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#define set_pud(pudp, pud) \
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do { \
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*pudp = pud; \
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flush_pmd_entry(pudp); \
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} while (0)
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static inline pmd_t *pud_page_vaddr(pud_t pud)
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{
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return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
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}
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/* Find an entry in the second-level page table.. */
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#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
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{
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return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
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}
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#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
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#define copy_pmd(pmdpd,pmdps) \
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do { \
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*pmdpd = *pmdps; \
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flush_pmd_entry(pmdpd); \
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} while (0)
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#define pmd_clear(pmdp) \
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do { \
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*pmdp = __pmd(0); \
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clean_pmd_entry(pmdp); \
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} while (0)
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#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_PGTABLE_3LEVEL_H */
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@ -65,7 +65,11 @@ extern struct processor {
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* Set a possibly extended PTE. Non-extended PTEs should
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* ignore 'ext'.
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*/
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#ifdef CONFIG_ARM_LPAE
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void (*set_pte_ext)(pte_t *ptep, pte_t pte);
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#else
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void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext);
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#endif
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/* Suspend/resume */
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unsigned int suspend_size;
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@ -79,7 +83,11 @@ extern void cpu_proc_fin(void);
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extern int cpu_do_idle(void);
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extern void cpu_dcache_clean_area(void *, int);
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extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
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#ifdef CONFIG_ARM_LPAE
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extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
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#else
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extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
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#endif
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extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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/* These three are private to arch/arm/kernel/suspend.c */
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@ -107,6 +115,18 @@ extern void cpu_resume(void);
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#ifdef CONFIG_ARM_LPAE
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#define cpu_get_pgd() \
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({ \
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unsigned long pg, pg2; \
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__asm__("mrrc p15, 0, %0, %1, c2" \
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: "=r" (pg), "=r" (pg2) \
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: \
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: "cc"); \
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pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \
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(pgd_t *)phys_to_virt(pg); \
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})
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#else
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#define cpu_get_pgd() \
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({ \
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unsigned long pg; \
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@ -115,6 +135,7 @@ extern void cpu_resume(void);
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pg &= ~0x3fff; \
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(pgd_t *)phys_to_virt(pg); \
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})
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#endif
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#endif
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@ -64,7 +64,7 @@ void __check_kvm_seq(struct mm_struct *mm)
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} while (seq != init_mm.context.kvm_seq);
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}
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#ifndef CONFIG_SMP
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#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
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/*
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* Section support is unsafe on SMP - If you iounmap and ioremap a region,
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* the other CPUs will not see this change until their next context switch.
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@ -202,11 +202,13 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
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unsigned long addr;
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struct vm_struct * area;
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#ifndef CONFIG_ARM_LPAE
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/*
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* High mappings must be supersection aligned
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*/
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if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
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return NULL;
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#endif
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/*
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* Don't allow RAM to be mapped - this causes problems with ARMv6+
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@ -228,7 +230,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
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return NULL;
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addr = (unsigned long)area->addr;
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#ifndef CONFIG_SMP
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#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
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if (DOMAIN_IO == 0 &&
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(((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
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cpu_is_xsc3()) && pfn >= 0x100000 &&
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@ -320,7 +322,7 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
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void __iounmap(volatile void __iomem *io_addr)
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{
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void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
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#ifndef CONFIG_SMP
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#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
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struct vm_struct **p, *tmp;
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/*
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@ -10,6 +10,7 @@
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#include <linux/mm.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/slab.h>
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#include <asm/pgalloc.h>
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#include <asm/page.h>
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@ -17,6 +18,14 @@
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#include "mm.h"
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#ifdef CONFIG_ARM_LPAE
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#define __pgd_alloc() kmalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL)
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#define __pgd_free(pgd) kfree(pgd)
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#else
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#define __pgd_alloc() (pgd_t *)__get_free_pages(GFP_KERNEL, 2)
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#define __pgd_free(pgd) free_pages((unsigned long)pgd, 2)
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#endif
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/*
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* need to get a 16k page for level 1
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*/
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@ -27,7 +36,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
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pmd_t *new_pmd, *init_pmd;
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pte_t *new_pte, *init_pte;
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new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
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new_pgd = __pgd_alloc();
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if (!new_pgd)
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goto no_pgd;
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@ -42,10 +51,25 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
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clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
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#ifdef CONFIG_ARM_LPAE
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/*
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* Allocate PMD table for modules and pkmap mappings.
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*/
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new_pud = pud_alloc(mm, new_pgd + pgd_index(MODULES_VADDR),
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MODULES_VADDR);
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if (!new_pud)
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goto no_pud;
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new_pmd = pmd_alloc(mm, new_pud, 0);
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if (!new_pmd)
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goto no_pmd;
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#endif
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if (!vectors_high()) {
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/*
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* On ARM, first page must always be allocated since it
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* contains the machine vectors.
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* contains the machine vectors. The vectors are always high
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* with LPAE.
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*/
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new_pud = pud_alloc(mm, new_pgd, 0);
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if (!new_pud)
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@ -74,7 +98,7 @@ no_pte:
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no_pmd:
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pud_free(mm, new_pud);
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no_pud:
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free_pages((unsigned long)new_pgd, 2);
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__pgd_free(new_pgd);
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no_pgd:
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return NULL;
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}
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@ -111,5 +135,24 @@ no_pud:
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pgd_clear(pgd);
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pud_free(mm, pud);
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no_pgd:
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free_pages((unsigned long) pgd_base, 2);
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#ifdef CONFIG_ARM_LPAE
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/*
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* Free modules/pkmap or identity pmd tables.
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*/
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for (pgd = pgd_base; pgd < pgd_base + PTRS_PER_PGD; pgd++) {
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if (pgd_none_or_clear_bad(pgd))
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continue;
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if (pgd_val(*pgd) & L_PGD_SWAPPER)
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continue;
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pud = pud_offset(pgd, 0);
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if (pud_none_or_clear_bad(pud))
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continue;
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pmd = pmd_offset(pud, 0);
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pud_clear(pud);
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pmd_free(mm, pmd);
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pgd_clear(pgd);
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pud_free(mm, pud);
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}
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#endif
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__pgd_free(pgd_base);
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}
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