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memory-barriers.txt: Fix typo in pairing example

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In the "general barrier pairing with implicit control depdendency"
example, the last write by CPU 1 was meant to change variable x and not
y. The example would be pretty uninteresting if no CPU ever changes x
and the variable was initialized to zero.

Signed-off-by: Scott Tsai <scottt@scottt.tw>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
This commit is contained in:
Scott Tsai 2017-09-20 02:16:00 +08:00 committed by Paul E. McKenney
parent 0902b1f44a
commit d92f842bb3
1 changed files with 1 additions and 1 deletions
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Documentation/memory-barriers.txt
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@ -947,7 +947,7 @@ Or even:
=============== =============================== =============== ===============================
r1 = READ_ONCE(y); r1 = READ_ONCE(y);
<general barrier> <general barrier>
WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) { WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
<implicit control dependency> <implicit control dependency>
WRITE_ONCE(y, 1); WRITE_ONCE(y, 1);
} }