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https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next into drm-fixes
* 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next: drm/nvc0: improve vm flush function drm/nv50-nvc0: remove some code that doesn't belong here drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac drm/nouveau: quirk for XFX GT-240X-YA drm/nv50-nvc0: work around an evo channel hang that some people see drm/nouveau: implement init table opcode 0x5c drm/nouveau: fix oops on unload with disabled LVDS panel nv30: Fix parsing of perf table drm/nouveau: correct memtiming table parsing for nv4x
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commit
d85023a3cd
@ -269,7 +269,7 @@ struct init_tbl_entry {
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int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
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};
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static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
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static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
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#define MACRO_INDEX_SIZE 2
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#define MACRO_SIZE 8
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@ -2010,6 +2010,27 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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return 3;
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}
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static int
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init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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{
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/*
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* INIT_JUMP opcode: 0x5C ('\')
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*
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* offset (8 bit): opcode
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* offset + 1 (16 bit): offset (in bios)
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*
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* Continue execution of init table from 'offset'
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*/
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uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
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if (!iexec->execute)
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return 3;
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BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
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return jmp_offset - offset;
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}
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static int
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init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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{
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@ -3659,6 +3680,7 @@ static struct init_tbl_entry itbl_entry[] = {
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{ "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
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/* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
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{ "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
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{ "INIT_JUMP" , 0x5C, init_jump },
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{ "INIT_I2C_IF" , 0x5E, init_i2c_if },
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{ "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
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{ "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
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@ -3700,8 +3722,7 @@ static struct init_tbl_entry itbl_entry[] = {
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#define MAX_TABLE_OPS 1000
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static int
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parse_init_table(struct nvbios *bios, unsigned int offset,
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struct init_exec *iexec)
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parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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{
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/*
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* Parses all commands in an init table.
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@ -6333,6 +6354,32 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
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}
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}
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/* XFX GT-240X-YA
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*
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* So many things wrong here, replace the entire encoder table..
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*/
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if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
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if (idx == 0) {
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*conn = 0x02001300; /* VGA, connector 1 */
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*conf = 0x00000028;
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} else
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if (idx == 1) {
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*conn = 0x01010312; /* DVI, connector 0 */
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*conf = 0x00020030;
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} else
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if (idx == 2) {
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*conn = 0x01010310; /* VGA, connector 0 */
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*conf = 0x00000028;
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} else
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if (idx == 3) {
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*conn = 0x02022362; /* HDMI, connector 2 */
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*conf = 0x00020010;
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} else {
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*conn = 0x0000000e; /* EOL */
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*conf = 0x00000000;
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}
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}
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return true;
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}
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@ -1190,7 +1190,7 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
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extern int nv50_graph_unload_context(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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extern void nv50_graph_tlb_flush(struct drm_device *dev);
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extern void nv86_graph_tlb_flush(struct drm_device *dev);
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extern void nv84_graph_tlb_flush(struct drm_device *dev);
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extern struct nouveau_enum nv50_data_error_names[];
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/* nvc0_graph.c */
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@ -552,6 +552,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
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u8 tRC; /* Byte 9 */
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u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
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u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
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u8 magic_number = 0; /* Yeah... sorry*/
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u8 *mem = NULL, *entry;
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int i, recordlen, entries;
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@ -596,6 +597,12 @@ nouveau_mem_timing_init(struct drm_device *dev)
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if (!memtimings->timing)
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return;
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/* Get "some number" from the timing reg for NV_40
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* Used in calculations later */
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if(dev_priv->card_type == NV_40) {
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magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
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}
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entry = mem + mem[1];
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for (i = 0; i < entries; i++, entry += recordlen) {
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struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
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@ -635,36 +642,51 @@ nouveau_mem_timing_init(struct drm_device *dev)
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/* XXX: I don't trust the -1's and +1's... they must come
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* from somewhere! */
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timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
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timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
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tUNK_18 << 16 |
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(tUNK_1 + tUNK_19 + 1) << 8 |
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(tUNK_2 - 1));
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(tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
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if(dev_priv->chipset == 0xa8) {
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timing->reg_100224 |= (tUNK_2 - 1);
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} else {
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timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
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}
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timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
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if(recordlen > 19) {
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timing->reg_100228 += (tUNK_19 - 1) << 24;
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}/* I cannot back-up this else-statement right now
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else {
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timing->reg_100228 += tUNK_12 << 24;
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}*/
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if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
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timing->reg_100228 |= (tUNK_19 - 1) << 24;
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}
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if(dev_priv->card_type == NV_40) {
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/* NV40: don't know what the rest of the regs are..
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* And don't need to know either */
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timing->reg_100228 |= 0x20200000 | magic_number << 24;
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} else if(dev_priv->card_type >= NV_50) {
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/* XXX: reg_10022c */
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timing->reg_10022c = tUNK_2 - 1;
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timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
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tUNK_13 << 8 | tUNK_13);
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/* XXX: +6? */
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timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
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timing->reg_100234 = (tRAS << 24 | tRC);
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timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
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if(dev_priv->chipset < 0xa3) {
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timing->reg_100234 |= (tUNK_2 + 2) << 8;
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} else {
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/* XXX: +6? */
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timing->reg_100234 |= (tUNK_19 + 6) << 8;
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}
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/* XXX; reg_100238, reg_10023c
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* reg: 0x00??????
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* reg_10023c:
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* 0 for pre-NV50 cards
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* 0x????0202 for NV50+ cards (empirical evidence) */
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if(dev_priv->card_type >= NV_50) {
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* reg_100238: 0x00??????
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* reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
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timing->reg_10023c = 0x202;
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if(dev_priv->chipset < 0xa3) {
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timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
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} else {
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/* currently unknown
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* 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
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}
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}
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NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
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@ -134,7 +134,7 @@ nouveau_perf_init(struct drm_device *dev)
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case 0x13:
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case 0x15:
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perflvl->fanspeed = entry[55];
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perflvl->voltage = entry[56];
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perflvl->voltage = (recordlen > 56) ? entry[56] : 0;
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perflvl->core = ROM32(entry[1]) * 10;
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perflvl->memory = ROM32(entry[5]) * 20;
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break;
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@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.destroy_context = nv50_graph_destroy_context;
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engine->graph.load_context = nv50_graph_load_context;
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engine->graph.unload_context = nv50_graph_unload_context;
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if (dev_priv->chipset != 0x86)
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if (dev_priv->chipset == 0x50 ||
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dev_priv->chipset == 0xac)
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engine->graph.tlb_flush = nv50_graph_tlb_flush;
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else {
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/* from what i can see nvidia do this on every
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* pre-NVA3 board except NVAC, but, we've only
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* ever seen problems on NV86
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*/
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engine->graph.tlb_flush = nv86_graph_tlb_flush;
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}
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else
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engine->graph.tlb_flush = nv84_graph_tlb_flush;
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engine->fifo.channels = 128;
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engine->fifo.init = nv50_fifo_init;
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engine->fifo.takedown = nv50_fifo_takedown;
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@ -581,12 +581,13 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
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int head = nv_encoder->restore.head;
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if (nv_encoder->dcb->type == OUTPUT_LVDS) {
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struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
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if (native_mode)
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call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
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native_mode->clock);
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else
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NV_ERROR(dev, "Not restoring LVDS without native mode\n");
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struct nouveau_connector *connector =
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nouveau_encoder_connector_get(nv_encoder);
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if (connector && connector->native_mode)
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call_lvds_script(dev, nv_encoder->dcb, head,
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LVDS_PANEL_ON,
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connector->native_mode->clock);
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} else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
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int clock = nouveau_hw_pllvals_to_clk
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@ -469,9 +469,6 @@ nv50_crtc_wait_complete(struct drm_crtc *crtc)
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start = ptimer->read(dev);
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do {
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nv_wr32(dev, 0x61002c, 0x370);
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nv_wr32(dev, 0x000140, 1);
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if (nv_ro32(disp->ntfy, 0x000))
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return 0;
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} while (ptimer->read(dev) - start < 2000000000ULL);
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@ -186,6 +186,7 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
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nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
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evo->dma.max = (4096/4) - 2;
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evo->dma.max &= ~7;
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evo->dma.put = 0;
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evo->dma.cur = evo->dma.put;
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evo->dma.free = evo->dma.max - evo->dma.cur;
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@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev)
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}
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void
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nv86_graph_tlb_flush(struct drm_device *dev)
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nv84_graph_tlb_flush(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
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@ -104,20 +104,26 @@ nvc0_vm_flush(struct nouveau_vm *vm)
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct drm_device *dev = vm->dev;
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struct nouveau_vm_pgd *vpgd;
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u32 r100c80, engine;
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u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5;
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pinstmem->flush(vm->dev);
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if (vm == dev_priv->chan_vm)
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engine = 1;
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else
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engine = 5;
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spin_lock(&dev_priv->ramin_lock);
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list_for_each_entry(vpgd, &vm->pgd_list, head) {
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r100c80 = nv_rd32(dev, 0x100c80);
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/* looks like maybe a "free flush slots" counter, the
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* faster you write to 0x100cbc to more it decreases
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*/
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if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
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NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
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nv_rd32(dev, 0x100c80), engine);
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}
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nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
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nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
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if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80))
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NV_ERROR(dev, "vm flush timeout eng %d\n", engine);
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/* wait for flush to be queued? */
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if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
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NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
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nv_rd32(dev, 0x100c80), engine);
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}
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}
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spin_unlock(&dev_priv->ramin_lock);
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}
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