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MIPS: Alchemy: DB1200: Remove custom wait implementation
While playing with the out-of-tree MAE driver module, the system would panic after a while in the db1200 custom wait code after wakeup due to a clobbered k0 register being used as target address of a store op. Remove the custom wait implementation and revert back to the Alchemy- recommended implementation already set as default. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -60,43 +60,6 @@ void __init board_setup(void)
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wmb();
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}
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/* use the hexleds to count the number of times the cpu has entered
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* wait, the dots to indicate whether the CPU is currently idle or
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* active (dots off = sleeping, dots on = working) for cases where
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* the number doesn't change for a long(er) period of time.
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*/
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static void db1200_wait(void)
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{
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__asm__(" .set push \n"
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" .set mips3 \n"
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" .set noreorder \n"
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" cache 0x14, 0(%0) \n"
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" cache 0x14, 32(%0) \n"
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" cache 0x14, 64(%0) \n"
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/* dots off: we're about to call wait */
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" lui $26, 0xb980 \n"
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" ori $27, $0, 3 \n"
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" sb $27, 0x18($26) \n"
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" sync \n"
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" nop \n"
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" wait \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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/* dots on: there's work to do, increment cntr */
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" lui $26, 0xb980 \n"
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" sb $0, 0x18($26) \n"
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" lui $26, 0xb9c0 \n"
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" lb $27, 0($26) \n"
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" addiu $27, $27, 1 \n"
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" sb $27, 0($26) \n"
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" sync \n"
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" .set pop \n"
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: : "r" (db1200_wait));
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}
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static int __init db1200_arch_init(void)
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{
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/* GPIO7 is low-level triggered CPLD cascade */
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@ -110,9 +73,6 @@ static int __init db1200_arch_init(void)
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irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
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irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
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if (cpu_wait)
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cpu_wait = db1200_wait;
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return 0;
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}
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arch_initcall(db1200_arch_init);
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