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interconnect: qcom: Add EPSS L3 support on SM8250

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Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SM8250 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200801123049.32398-6-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
This commit is contained in:
Sibi Sankar 2020-09-08 16:29:01 +03:00 committed by Georgi Djakov
parent c4877059e0
commit d7e19be60b
2 changed files with 25 additions and 0 deletions
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23
drivers/interconnect/qcom/osm-l3.c
View File

@ -17,6 +17,7 @@
#include "sc7180.h" #include "sc7180.h"
#include "sdm845.h" #include "sdm845.h"
#include "sm8150.h" #include "sm8150.h"
#include "sm8250.h"
#define LUT_MAX_ENTRIES 40U #define LUT_MAX_ENTRIES 40U
#define LUT_SRC GENMASK(31, 30) #define LUT_SRC GENMASK(31, 30)
@ -29,6 +30,11 @@
#define OSM_REG_FREQ_LUT 0x110 #define OSM_REG_FREQ_LUT 0x110
#define OSM_REG_PERF_STATE 0x920 #define OSM_REG_PERF_STATE 0x920
/* EPSS Register offsets */
#define EPSS_LUT_ROW_SIZE 4
#define EPSS_REG_FREQ_LUT 0x100
#define EPSS_REG_PERF_STATE 0x320
#define OSM_L3_MAX_LINKS 1 #define OSM_L3_MAX_LINKS 1
#define to_qcom_provider(_provider) \ #define to_qcom_provider(_provider) \
@ -123,6 +129,22 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
.reg_perf_state = OSM_REG_PERF_STATE, .reg_perf_state = OSM_REG_PERF_STATE,
}; };
DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
static struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
};
static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
.nodes = sm8250_epss_l3_nodes,
.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_PERF_STATE,
};
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
{ {
struct qcom_osm_l3_icc_provider *qp; struct qcom_osm_l3_icc_provider *qp;
@ -288,6 +310,7 @@ static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
{ } { }
}; };
MODULE_DEVICE_TABLE(of, osm_l3_of_match); MODULE_DEVICE_TABLE(of, osm_l3_of_match);

2
drivers/interconnect/qcom/sm8250.h
View File

@ -158,5 +158,7 @@
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147 #define SM8250_SLAVE_VSENSE_CTRL_CFG 147
#define SM8250_SNOC_CNOC_MAS 148 #define SM8250_SNOC_CNOC_MAS 148
#define SM8250_SNOC_CNOC_SLV 149 #define SM8250_SNOC_CNOC_SLV 149
#define SM8250_MASTER_EPSS_L3_APPS 150
#define SM8250_SLAVE_EPSS_L3 151
#endif #endif