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x86: use native register access for native tlb flushing

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currently these are paravirtulaized, doesn't appear any callers rely on
this (no pv_ops backends are using native_tlb and overriding cr3/4
access).

[ Impact: fix lockdep warning with paravirt and function tracer ]

Signed-off-by: Chris Wright <chrisw@sous-sol.org>
LKML-Reference: <20090423172138.GR3036@sequoia.sous-sol.org>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
This commit is contained in:
Chris Wright 2009-04-23 10:21:38 -07:00 committed by Steven Rostedt
parent 75db37d2f4
commit d7285c6b5c
1 changed files with 4 additions and 4 deletions
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8
arch/x86/include/asm/tlbflush.h
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@ -17,7 +17,7 @@
static inline void __native_flush_tlb(void)
{
write_cr3(read_cr3());
native_write_cr3(native_read_cr3());
}
static inline void __native_flush_tlb_global(void)
@ -32,11 +32,11 @@ static inline void __native_flush_tlb_global(void)
*/
raw_local_irq_save(flags);
cr4 = read_cr4();
cr4 = native_read_cr4();
/* clear PGE */
write_cr4(cr4 & ~X86_CR4_PGE);
native_write_cr4(cr4 & ~X86_CR4_PGE);
/* write old PGE again and flush TLBs */
write_cr4(cr4);
native_write_cr4(cr4);
raw_local_irq_restore(flags);
}