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scsi: mpt3sas: Force PCIe scatterlist allocations to be within same 4 GB region
According to the MPI specification, PCIe SGL buffers can not cross a 4 GB boundary. While allocating, if any buffer crosses the 4 GB boundary, then: - Release the already allocated memory pools; and - Reallocate them by changing the DMA coherent mask to 32-bit Link: https://lore.kernel.org/r/20210305102904.7560-2-suganath-prabu.subramani@broadcom.com Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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a1c4d77413
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@ -2905,23 +2905,22 @@ static int
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_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
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{
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struct sysinfo s;
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int dma_mask;
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if (ioc->is_mcpu_endpoint ||
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sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
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dma_get_required_mask(&pdev->dev) <= 32)
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dma_mask = 32;
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ioc->dma_mask = 32;
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/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
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else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
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dma_mask = 63;
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ioc->dma_mask = 63;
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else
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dma_mask = 64;
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ioc->dma_mask = 64;
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) ||
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dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)))
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) ||
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dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)))
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return -ENODEV;
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if (dma_mask > 32) {
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if (ioc->dma_mask > 32) {
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ioc->base_add_sg_single = &_base_add_sg_single_64;
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ioc->sge_size = sizeof(Mpi2SGESimple64_t);
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} else {
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@ -2931,7 +2930,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
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si_meminfo(&s);
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ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
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dma_mask, convert_to_kb(s.totalram));
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ioc->dma_mask, convert_to_kb(s.totalram));
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return 0;
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}
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@ -5337,10 +5336,10 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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dma_pool_free(ioc->pcie_sgl_dma_pool,
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ioc->pcie_sg_lookup[i].pcie_sgl,
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ioc->pcie_sg_lookup[i].pcie_sgl_dma);
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ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
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}
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dma_pool_destroy(ioc->pcie_sgl_dma_pool);
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}
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if (ioc->config_page) {
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dexitprintk(ioc,
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ioc_info(ioc, "config_page(0x%p): free\n",
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@ -5398,6 +5397,89 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
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return 0;
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}
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/**
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* _base_reduce_hba_queue_depth- Retry with reduced queue depth
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* @ioc: Adapter object
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*
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* Return: 0 for success, non-zero for failure.
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**/
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static inline int
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_base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
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{
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int reduce_sz = 64;
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if ((ioc->hba_queue_depth - reduce_sz) >
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(ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
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ioc->hba_queue_depth -= reduce_sz;
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return 0;
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} else
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return -ENOMEM;
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}
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/**
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* _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
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* for pcie sgl pools.
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* @ioc: Adapter object
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* @sz: DMA Pool size
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* @ct: Chain tracker
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* Return: 0 for success, non-zero for failure.
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*/
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static int
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_base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
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{
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int i = 0, j = 0;
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struct chain_tracker *ct;
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ioc->pcie_sgl_dma_pool =
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dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
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ioc->page_size, 0);
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if (!ioc->pcie_sgl_dma_pool) {
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ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
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return -ENOMEM;
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}
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ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
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ioc->chains_per_prp_buffer =
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min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
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for (i = 0; i < ioc->scsiio_depth; i++) {
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ioc->pcie_sg_lookup[i].pcie_sgl =
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dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
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&ioc->pcie_sg_lookup[i].pcie_sgl_dma);
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if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
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ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
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return -EAGAIN;
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}
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if (!mpt3sas_check_same_4gb_region(
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(long)ioc->pcie_sg_lookup[i].pcie_sgl, sz)) {
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ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
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ioc->pcie_sg_lookup[i].pcie_sgl,
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(unsigned long long)
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ioc->pcie_sg_lookup[i].pcie_sgl_dma);
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ioc->use_32bit_dma = true;
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return -EAGAIN;
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}
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for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
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ct = &ioc->chain_lookup[i].chains_per_smid[j];
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ct->chain_buffer =
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ioc->pcie_sg_lookup[i].pcie_sgl +
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(j * ioc->chain_segment_sz);
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ct->chain_buffer_dma =
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ioc->pcie_sg_lookup[i].pcie_sgl_dma +
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(j * ioc->chain_segment_sz);
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}
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}
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dinitprintk(ioc, ioc_info(ioc,
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"PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
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ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
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dinitprintk(ioc, ioc_info(ioc,
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"Number of chains can fit in a PRP page(%d)\n",
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ioc->chains_per_prp_buffer));
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return 0;
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}
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/**
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* base_alloc_rdpq_dma_pool - Allocating DMA'able memory
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* for reply queues.
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@ -5496,7 +5578,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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unsigned short sg_tablesize;
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u16 sge_size;
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int i, j;
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int ret = 0;
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int ret = 0, rc = 0;
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struct chain_tracker *ct;
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dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
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@ -5801,6 +5883,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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* be required for NVMe PRP's, only each set of NVMe blocks will be
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* contiguous, so a new set is allocated for each possible I/O.
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*/
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ioc->chains_per_prp_buffer = 0;
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if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
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nvme_blocks_needed =
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@ -5815,43 +5898,11 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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goto out;
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}
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sz = nvme_blocks_needed * ioc->page_size;
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ioc->pcie_sgl_dma_pool =
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dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
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if (!ioc->pcie_sgl_dma_pool) {
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ioc_info(ioc, "PCIe SGL pool: dma_pool_create failed\n");
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goto out;
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}
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ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
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ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
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ioc->chains_needed_per_io);
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for (i = 0; i < ioc->scsiio_depth; i++) {
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ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
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ioc->pcie_sgl_dma_pool, GFP_KERNEL,
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&ioc->pcie_sg_lookup[i].pcie_sgl_dma);
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if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
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ioc_info(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
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goto out;
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}
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for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
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ct = &ioc->chain_lookup[i].chains_per_smid[j];
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ct->chain_buffer =
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ioc->pcie_sg_lookup[i].pcie_sgl +
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(j * ioc->chain_segment_sz);
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ct->chain_buffer_dma =
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ioc->pcie_sg_lookup[i].pcie_sgl_dma +
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(j * ioc->chain_segment_sz);
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}
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}
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dinitprintk(ioc,
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ioc_info(ioc, "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
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ioc->scsiio_depth, sz,
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(sz * ioc->scsiio_depth) / 1024));
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dinitprintk(ioc,
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ioc_info(ioc, "Number of chains can fit in a PRP page(%d)\n",
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ioc->chains_per_prp_buffer));
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rc = _base_allocate_pcie_sgl_pool(ioc, sz);
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if (rc == -ENOMEM)
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return -ENOMEM;
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else if (rc == -EAGAIN)
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goto try_32bit_dma;
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total_sz += sz * ioc->scsiio_depth;
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}
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@ -6021,6 +6072,19 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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ioc->shost->sg_tablesize);
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return 0;
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try_32bit_dma:
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_base_release_memory_pools(ioc);
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if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
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/* Change dma coherent mask to 32 bit and reallocate */
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if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
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pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
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pci_name(ioc->pdev));
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return -ENODEV;
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}
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} else if (_base_reduce_hba_queue_depth(ioc) != 0)
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return -ENOMEM;
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goto retry_allocation;
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out:
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return -ENOMEM;
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}
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@ -7681,6 +7745,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
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ioc->rdpq_array_enable_assigned = 0;
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ioc->use_32bit_dma = false;
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ioc->dma_mask = 64;
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if (ioc->is_aero_ioc)
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ioc->base_readl = &_base_readl_aero;
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else
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@ -1371,6 +1371,7 @@ struct MPT3SAS_ADAPTER {
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u16 thresh_hold;
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u8 high_iops_queues;
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u32 drv_support_bitmap;
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u32 dma_mask;
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bool enable_sdev_max_qd;
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bool use_32bit_dma;
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