renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2025-01-20 03:24:03 +08:00
Code

drm/omap: fix HDMI sync polarities

Browse Source 
While implementing writeback support, odd behavior of WBDELAYCOUNT was
observed with the combination of WB capture and HDMI. The result of the
debugging was that the HDMI sync polarities are not set correctly.

The current code sets the sync polarities going from HDMI WP to DISPC
according to the video mode used, which seems to work normally fine, but
causes problems with WB as WB expects the syncs to be active-high.

This patch changes the HDMI sync polarities so that the DISPC always
gets active-high syncs from HDMI WP, and the HDMI core gets sync
polarities according to the used video mode.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
This commit is contained in:
Tomi Valkeinen 2016-05-27 13:49:05 +03:00
parent 5f6ab8ca18
commit d5e7efad7b
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
View File

@ -147,15 +147,17 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
struct videomode *vm)
{
u32 r;
bool vsync_pol, hsync_pol;
bool vsync_inv, hsync_inv;
DSSDBG("Enter hdmi_wp_video_config_interface\n");
vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
r = FLD_MOD(r, vsync_pol, 7, 7);
r = FLD_MOD(r, hsync_pol, 6, 6);
r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */
r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */
r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */
r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */
r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);