mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 10:44:14 +08:00
drm/nvc0: implement support for copy engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
7ff5441e55
commit
d5a27370b5
@ -20,7 +20,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv40_graph.o nv50_graph.o nvc0_graph.o \
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nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
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nv84_crypt.o \
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nva3_copy.o \
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nva3_copy.o nvc0_copy.o \
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nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
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nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
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nv50_cursor.o nv50_display.o \
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@ -1143,6 +1143,7 @@ extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
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/* nvc0_graph.c */
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extern int nvc0_graph_create(struct drm_device *);
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extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
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/* nv84_crypt.c */
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extern int nv84_crypt_create(struct drm_device *);
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@ -609,6 +609,10 @@ nouveau_card_init(struct drm_device *dev)
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break;
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}
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break;
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case NV_C0:
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nvc0_copy_create(dev, 0);
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nvc0_copy_create(dev, 1);
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break;
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default:
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break;
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}
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243
drivers/gpu/drm/nouveau/nvc0_copy.c
Normal file
243
drivers/gpu/drm/nouveau/nvc0_copy.c
Normal file
@ -0,0 +1,243 @@
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/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_util.h"
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#include "nouveau_vm.h"
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#include "nouveau_ramht.h"
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#include "nvc0_copy.fuc.h"
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struct nvc0_copy_engine {
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struct nouveau_exec_engine base;
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u32 irq;
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u32 pmc;
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u32 fuc;
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u32 ctx;
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};
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static int
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nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_gpuobj *ctx = NULL;
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int ret;
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ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
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NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER |
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NVOBJ_FLAG_ZERO_ALLOC, &ctx);
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if (ret)
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return ret;
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nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));
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nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));
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dev_priv->engine.instmem.flush(dev);
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chan->engctx[engine] = ctx;
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return 0;
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}
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static int
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nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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return 0;
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}
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static void
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nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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u32 inst;
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inst = (chan->ramin->vinst >> 12);
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inst |= 0x40000000;
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/* disable fifo access */
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nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
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/* mark channel as unloaded if it's currently active */
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if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
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nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
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/* mark next channel as invalid if it's about to be loaded */
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if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
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nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
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/* restore fifo access */
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nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
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nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
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nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
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nouveau_gpuobj_ref(NULL, &ctx);
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chan->engctx[engine] = ctx;
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}
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static int
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nvc0_copy_init(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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int i;
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nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
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nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
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nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
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nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
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for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
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nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
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nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
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for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
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nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
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}
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nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
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nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
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nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
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return 0;
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}
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static int
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nvc0_copy_fini(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
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/* trigger fuc context unload */
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nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
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nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
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nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
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return 0;
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}
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static struct nouveau_enum nvc0_copy_isr_error_name[] = {
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{ 0x0001, "ILLEGAL_MTHD" },
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{ 0x0002, "INVALID_ENUM" },
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{ 0x0003, "INVALID_BITFIELD" },
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{}
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};
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static void
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nvc0_copy_isr(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
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u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
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u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
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u32 chid = nvc0_graph_isr_chid(dev, inst);
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u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
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u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
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u32 mthd = (addr & 0x07ff) << 2;
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u32 subc = (addr & 0x3800) >> 11;
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u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
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if (stat & 0x00000040) {
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NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
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nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
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printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
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chid, inst, subc, mthd, data);
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nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
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stat &= ~0x00000040;
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}
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if (stat) {
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NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
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nv_wr32(dev, pcopy->fuc + 0x004, stat);
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}
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}
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static void
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nvc0_copy_isr_0(struct drm_device *dev)
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{
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nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
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}
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static void
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nvc0_copy_isr_1(struct drm_device *dev)
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{
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nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
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}
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static void
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nvc0_copy_destroy(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, pcopy->irq);
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if (engine == NVOBJ_ENGINE_COPY0)
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NVOBJ_ENGINE_DEL(dev, COPY0);
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else
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NVOBJ_ENGINE_DEL(dev, COPY1);
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kfree(pcopy);
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}
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int
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nvc0_copy_create(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy;
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pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
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if (!pcopy)
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return -ENOMEM;
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pcopy->base.destroy = nvc0_copy_destroy;
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pcopy->base.init = nvc0_copy_init;
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pcopy->base.fini = nvc0_copy_fini;
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pcopy->base.context_new = nvc0_copy_context_new;
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pcopy->base.context_del = nvc0_copy_context_del;
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pcopy->base.object_new = nvc0_copy_object_new;
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if (engine == 0) {
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pcopy->irq = 5;
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pcopy->pmc = 0x00000040;
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pcopy->fuc = 0x104000;
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pcopy->ctx = 0x0230;
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nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
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NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
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NVOBJ_CLASS(dev, 0x90b5, COPY0);
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} else {
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pcopy->irq = 6;
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pcopy->pmc = 0x00000080;
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pcopy->fuc = 0x105000;
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pcopy->ctx = 0x0240;
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nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
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NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
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NVOBJ_CLASS(dev, 0x90b8, COPY1);
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}
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return 0;
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}
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527
drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
Normal file
527
drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
Normal file
@ -0,0 +1,527 @@
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uint32_t nvc0_pcopy_data[] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00010000,
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0x00000000,
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0x00000000,
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0x00010040,
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0x0001019f,
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0x00000000,
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0x00010050,
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0x000101a1,
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0x00000000,
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0x00070080,
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0x0000001c,
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0xfffff000,
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0x00000020,
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0xfff80000,
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0x00000024,
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0xffffe000,
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0x00000028,
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0xfffff800,
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0x0000002c,
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0xfffff000,
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0x00000030,
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0xfff80000,
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0x00000034,
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0xffffe000,
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0x00070088,
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0x00000048,
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0xfffff000,
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0x0000004c,
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0xfff80000,
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0x00000050,
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0xffffe000,
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0x00000054,
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0xfffff800,
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0x00000058,
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0xfffff000,
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0x0000005c,
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0xfff80000,
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0x00000060,
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0xffffe000,
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0x000200c0,
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0x000104b8,
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0x00000000,
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0x00010541,
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0x00000000,
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0x000e00c3,
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0x00000010,
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0xffffff00,
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0x00000014,
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0x0000000f,
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0x0000003c,
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0xffffff00,
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0x00000040,
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0x0000000f,
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0x00000018,
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0xfff80000,
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0x00000044,
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0xfff80000,
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0x00000074,
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0xffff0000,
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0x00000078,
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0xffffe000,
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0x00000068,
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0xfccc0000,
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0x0000006c,
|
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0x00000000,
|
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0x00000070,
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0x00000000,
|
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0x00000004,
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0xffffff00,
|
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0x00000008,
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0x00000000,
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0x0000000c,
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0x00000000,
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0x00000800,
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};
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uint32_t nvc0_pcopy_code[] = {
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0x04fe04bd,
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0x3517f000,
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0xf10010fe,
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0xf1040017,
|
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0xf0fff327,
|
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0x22d00023,
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0x0c25f0c0,
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0xf40012d0,
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0x17f11031,
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0x27f01200,
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0x0012d003,
|
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0xf40031f4,
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0x0ef40028,
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0x8001cffd,
|
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0xf40812c4,
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0x21f4060b,
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0x0412c4ca,
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0xf5070bf4,
|
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0xc4010221,
|
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0x01d00c11,
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0xf101f840,
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0xfe770047,
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0x47f1004b,
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0x44cf2100,
|
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0x0144f000,
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0xb60444b6,
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0xf7f13040,
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0xf4b6061c,
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0x1457f106,
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0x00f5d101,
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0xb6043594,
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0x57fe0250,
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0x0145fe00,
|
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0x010052b7,
|
||||
0x00ff67f1,
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||||
0x56fd60bd,
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0x0253f004,
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0xf80545fa,
|
||||
0x0053f003,
|
||||
0xd100e7f0,
|
||||
0x549800fe,
|
||||
0x0845b600,
|
||||
0xb6015698,
|
||||
0x46fd1864,
|
||||
0x0047fe05,
|
||||
0xf00204b9,
|
||||
0x01f40643,
|
||||
0x0604fa09,
|
||||
0xfa060ef4,
|
||||
0x03f80504,
|
||||
0x27f100f8,
|
||||
0x23cf1400,
|
||||
0x1e3fc800,
|
||||
0xf4170bf4,
|
||||
0x21f40132,
|
||||
0x1e3af053,
|
||||
0xf00023d0,
|
||||
0x24d00147,
|
||||
0xcf00f880,
|
||||
0x3dc84023,
|
||||
0x090bf41e,
|
||||
0xf40131f4,
|
||||
0x37f05321,
|
||||
0x8023d002,
|
||||
0x37f100f8,
|
||||
0x32cf1900,
|
||||
0x0033cf40,
|
||||
0x07ff24e4,
|
||||
0xf11024b6,
|
||||
0xbd010057,
|
||||
0x5874bd64,
|
||||
0x57580056,
|
||||
0x0450b601,
|
||||
0xf40446b8,
|
||||
0x76bb4d08,
|
||||
0x0447b800,
|
||||
0xbb0f08f4,
|
||||
0x74b60276,
|
||||
0x0057bb03,
|
||||
0xbbdf0ef4,
|
||||
0x44b60246,
|
||||
0x0045bb03,
|
||||
0xfd014598,
|
||||
0x54b00453,
|
||||
0x201bf400,
|
||||
0x58004558,
|
||||
0x64b00146,
|
||||
0x091bf400,
|
||||
0xf4005380,
|
||||
0x32f4300e,
|
||||
0xf455f901,
|
||||
0x0ef40c01,
|
||||
0x0225f025,
|
||||
0xf10125f0,
|
||||
0xd0100047,
|
||||
0x43d00042,
|
||||
0x4027f040,
|
||||
0xcf0002d0,
|
||||
0x24f08002,
|
||||
0x0024b040,
|
||||
0xf1f71bf4,
|
||||
0xf01d0027,
|
||||
0x23d00137,
|
||||
0xf800f800,
|
||||
0x0027f100,
|
||||
0xf034bd22,
|
||||
0x23d00233,
|
||||
0xf400f800,
|
||||
0x01b0f030,
|
||||
0x0101b000,
|
||||
0xb00201b0,
|
||||
0x04980301,
|
||||
0x3045c71a,
|
||||
0xc70150b6,
|
||||
0x60b63446,
|
||||
0x3847c701,
|
||||
0xf40170b6,
|
||||
0x84bd0232,
|
||||
0x4ac494bd,
|
||||
0x0445b60f,
|
||||
0xa430b4bd,
|
||||
0x0f18f404,
|
||||
0xbbc0a5ff,
|
||||
0x31f400cb,
|
||||
0x220ef402,
|
||||
0xf00c1bf4,
|
||||
0xcbbb10c7,
|
||||
0x160ef400,
|
||||
0xf406a430,
|
||||
0xc7f00c18,
|
||||
0x00cbbb14,
|
||||
0xf1070ef4,
|
||||
0x380080c7,
|
||||
0x80b601c8,
|
||||
0x01b0b601,
|
||||
0xf404b5b8,
|
||||
0x90b6c308,
|
||||
0x0497b801,
|
||||
0xfdb208f4,
|
||||
0x06800065,
|
||||
0x1d08980e,
|
||||
0xf40068fd,
|
||||
0x64bd0502,
|
||||
0x800075fd,
|
||||
0x78fd1907,
|
||||
0x1057f100,
|
||||
0x0654b608,
|
||||
0xd00056d0,
|
||||
0x50b74057,
|
||||
0x06980800,
|
||||
0x0162b619,
|
||||
0x980864b6,
|
||||
0x72b60e07,
|
||||
0x0567fd01,
|
||||
0xb70056d0,
|
||||
0xb4010050,
|
||||
0x56d00060,
|
||||
0x0160b400,
|
||||
0xb44056d0,
|
||||
0x56d00260,
|
||||
0x0360b480,
|
||||
0xb7c056d0,
|
||||
0x98040050,
|
||||
0x56d01b06,
|
||||
0x1c069800,
|
||||
0xf44056d0,
|
||||
0x00f81030,
|
||||
0xc7075798,
|
||||
0x78c76879,
|
||||
0x0380b664,
|
||||
0xb06077c7,
|
||||
0x1bf40e76,
|
||||
0x0477f009,
|
||||
0xf00f0ef4,
|
||||
0x70b6027c,
|
||||
0x0947fd11,
|
||||
0x980677f0,
|
||||
0x5b980c5a,
|
||||
0x00abfd0e,
|
||||
0xbb01b7f0,
|
||||
0xb2b604b7,
|
||||
0xc4abff01,
|
||||
0x9805a7bb,
|
||||
0xe7f00d5d,
|
||||
0x04e8bb01,
|
||||
0xff01e2b6,
|
||||
0xd8bbb4de,
|
||||
0x01e0b605,
|
||||
0xbb0cef94,
|
||||
0xfefd02eb,
|
||||
0x026cf005,
|
||||
0x020860b7,
|
||||
0xd00864b6,
|
||||
0xb7bb006f,
|
||||
0x00cbbb04,
|
||||
0x98085f98,
|
||||
0xfbfd0e5b,
|
||||
0x01b7f000,
|
||||
0xb604b7bb,
|
||||
0xfbbb01b2,
|
||||
0x05f7bb00,
|
||||
0x5f98f0f9,
|
||||
0x01b7f009,
|
||||
0xb604b8bb,
|
||||
0xfbbb01b2,
|
||||
0x05f8bb00,
|
||||
0x78bbf0f9,
|
||||
0x0282b600,
|
||||
0xbb01b7f0,
|
||||
0xb9bb04b8,
|
||||
0x0b589804,
|
||||
0xbb01e7f0,
|
||||
0xe2b604e9,
|
||||
0xf48eff01,
|
||||
0xbb04f7bb,
|
||||
0x79bb00cf,
|
||||
0x0589bb00,
|
||||
0x90fcf0fc,
|
||||
0xbb00d9fd,
|
||||
0x89fd00ad,
|
||||
0x008ffd00,
|
||||
0xbb00a8bb,
|
||||
0x92b604a7,
|
||||
0x0497bb01,
|
||||
0x988069d0,
|
||||
0x58980557,
|
||||
0x00acbb04,
|
||||
0xb6007abb,
|
||||
0x84b60081,
|
||||
0x058bfd10,
|
||||
0x060062b7,
|
||||
0xb70067d0,
|
||||
0xd0040060,
|
||||
0x00f80068,
|
||||
0xb7026cf0,
|
||||
0xb6020260,
|
||||
0x57980864,
|
||||
0x0067d005,
|
||||
0x040060b7,
|
||||
0xb6045798,
|
||||
0x67d01074,
|
||||
0x0060b700,
|
||||
0x06579804,
|
||||
0xf80067d0,
|
||||
0xf900f900,
|
||||
0x0007f110,
|
||||
0x0604b608,
|
||||
0xf00001cf,
|
||||
0x1bf40114,
|
||||
0xfc10fcfa,
|
||||
0xc800f800,
|
||||
0x1bf40d34,
|
||||
0xd121f570,
|
||||
0x0c47f103,
|
||||
0x0644b608,
|
||||
0xb6020598,
|
||||
0x45d00450,
|
||||
0x4040d000,
|
||||
0xd00c57f0,
|
||||
0x40b78045,
|
||||
0x05980400,
|
||||
0x1054b601,
|
||||
0xb70045d0,
|
||||
0xf1050040,
|
||||
0xf00b0057,
|
||||
0x45d00153,
|
||||
0x4057f100,
|
||||
0x0154b640,
|
||||
0x808053f1,
|
||||
0xf14045d0,
|
||||
0xf1111057,
|
||||
0xd0131253,
|
||||
0x57f18045,
|
||||
0x53f11514,
|
||||
0x45d01716,
|
||||
0x0157f1c0,
|
||||
0x0153f026,
|
||||
0x080047f1,
|
||||
0xd00644b6,
|
||||
0x21f50045,
|
||||
0x47f103d1,
|
||||
0x44b6080c,
|
||||
0x02059806,
|
||||
0xd00045d0,
|
||||
0x57f04040,
|
||||
0x8045d004,
|
||||
0x040040b7,
|
||||
0xb6010598,
|
||||
0x45d01054,
|
||||
0x0040b700,
|
||||
0x0057f105,
|
||||
0x0045d003,
|
||||
0x111057f1,
|
||||
0x131253f1,
|
||||
0x984045d0,
|
||||
0x40b70305,
|
||||
0x45d00500,
|
||||
0x0157f100,
|
||||
0x0153f026,
|
||||
0x080047f1,
|
||||
0xd00644b6,
|
||||
0x00f80045,
|
||||
0x03d121f5,
|
||||
0xf4003fc8,
|
||||
0x21f50e0b,
|
||||
0x47f101af,
|
||||
0x0ef40200,
|
||||
0x1067f11e,
|
||||
0x0664b608,
|
||||
0x800177f0,
|
||||
0x07800e07,
|
||||
0x1d079819,
|
||||
0xd00067d0,
|
||||
0x44bd4067,
|
||||
0xbd0232f4,
|
||||
0x043fc854,
|
||||
0xf50a0bf4,
|
||||
0xf403a821,
|
||||
0x21f50a0e,
|
||||
0x49f0029c,
|
||||
0x0231f407,
|
||||
0xc82c57f0,
|
||||
0x0bf4083f,
|
||||
0xa821f50a,
|
||||
0x0a0ef403,
|
||||
0x029c21f5,
|
||||
0xf10849f0,
|
||||
0xb6080057,
|
||||
0x06980654,
|
||||
0x4056d01e,
|
||||
0xf14167f0,
|
||||
0xfd440063,
|
||||
0x54d00546,
|
||||
0x0c3fc800,
|
||||
0xf5070bf4,
|
||||
0xf803eb21,
|
||||
0x0027f100,
|
||||
0xf034bd22,
|
||||
0x23d00133,
|
||||
0x0000f800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
};
|
||||
@ -531,7 +531,7 @@ nvc0_graph_init(struct drm_device *dev, int engine)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user