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https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 01:34:00 +08:00
[PATCH] sky2: spelling fixes
Cosmetic cleanup's: mostly spelling fixes etc. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
shemminger@osdl.org
Jeff Garzik
parent
b2f5ad4fec
commit
d571b694df
@ -214,7 +214,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
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pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
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reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
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/* looks like this xl is back asswards .. */
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/* looks like this XL is back asswards .. */
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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
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reg1 |= PCI_Y2_PHY1_COMA;
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if (hw->ports > 1)
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@ -461,7 +461,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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if (ledover)
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gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
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/* Enable phy interrupt on autonegotiation complete (or link up) */
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/* Enable phy interrupt on auto-negotiation complete (or link up) */
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if (sky2->autoneg == AUTONEG_ENABLE)
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gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
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else
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@ -578,10 +578,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
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GMF_RX_CTRL_DEF);
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/* Flush Rx MAC FIFO on any flowcontrol or error */
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/* Flush Rx MAC FIFO on any flow control or error */
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reg = GMR_FS_ANY_ERR;
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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
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reg = 0; /* WA Dev #4115 */
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reg = 0; /* WA dev #4.115 */
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sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
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/* Set threshold to 0xa (64 bytes)
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@ -662,7 +662,7 @@ static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
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}
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/*
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* This is a workaround code taken from syskonnect sk98lin driver
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* This is a workaround code taken from SysKonnect sk98lin driver
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* to deal with chip bug on Yukon EC rev 0 in the wraparound case.
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*/
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static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
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@ -785,7 +785,7 @@ stopped:
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sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
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}
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/* Cleanout receive buffer area, assumes receiver hardware stopped */
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/* Clean out receive buffer area, assumes receiver hardware stopped */
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static void sky2_rx_clean(struct sky2_port *sky2)
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{
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unsigned i;
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@ -1174,7 +1174,7 @@ out_unlock:
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* Free ring elements from starting at tx_cons until "done"
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*
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* NB: the hardware will tell us about partial completion of multi-part
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* buffers; these are defered until completion.
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* buffers; these are deferred until completion.
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*/
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static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
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{
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@ -1182,7 +1182,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
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unsigned i;
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if (unlikely(netif_msg_tx_done(sky2)))
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printk(KERN_DEBUG "%s: tx done, upto %u\n",
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printk(KERN_DEBUG "%s: tx done, up to %u\n",
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dev->name, done);
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spin_lock(&sky2->tx_lock);
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@ -1282,7 +1282,7 @@ static int sky2_down(struct net_device *dev)
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sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
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sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
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/* turn off led's */
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/* turn off LED's */
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sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
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sky2_tx_clean(sky2);
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@ -1364,7 +1364,7 @@ static void sky2_link_up(struct sky2_port *sky2)
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if (netif_msg_link(sky2))
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printk(KERN_INFO PFX
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"%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
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"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
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sky2->netdev->name, sky2->speed,
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sky2->duplex == DUPLEX_FULL ? "full" : "half",
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(sky2->tx_pause && sky2->rx_pause) ? "both" :
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@ -1451,7 +1451,7 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
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}
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/*
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* Interrrupt from PHY are handled in tasklet (soft irq)
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* Interrupt from PHY are handled in tasklet (soft irq)
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* because accessing phy registers requires spin wait which might
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* cause excess interrupt latency.
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*/
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@ -1556,7 +1556,7 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu)
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/*
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* Receive one packet.
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* For small packets or errors, just reuse existing skb.
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* For larger pakects, get new buffer.
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* For larger packets, get new buffer.
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*/
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static struct sk_buff *sky2_receive(struct sky2_port *sky2,
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u16 length, u32 status)
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@ -1818,7 +1818,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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}
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if (status & Y2_IS_PCI_EXP) {
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/* PCI-Express uncorrectable Error occured */
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/* PCI-Express uncorrectable Error occurred */
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u32 pex_err;
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pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
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@ -2113,7 +2113,7 @@ static int sky2_reset(struct sky2_hw *hw)
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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
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sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
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else /* WA 4109 */
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else /* WA dev 4.109 */
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sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
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sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
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@ -2420,7 +2420,7 @@ static void sky2_set_multicast(struct net_device *dev)
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reg = gma_read16(hw, port, GM_RX_CTRL);
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reg |= GM_RXCR_UCF_ENA;
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if (dev->flags & IFF_PROMISC) /* promiscious */
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if (dev->flags & IFF_PROMISC) /* promiscuous */
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reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
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else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
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memset(filter, 0xff, sizeof(filter));
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@ -2833,7 +2833,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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}
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}
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#ifdef __BIG_ENDIAN
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/* byte swap decriptors in hardware */
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/* byte swap descriptors in hardware */
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{
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u32 reg;
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@ -356,11 +356,11 @@ enum {
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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enum {
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Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */
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Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
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Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
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Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
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Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
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Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */
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Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
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Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
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Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
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Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
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@ -410,7 +410,7 @@ enum {
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#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
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/* RAM Interface Registers */
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/* B3_RI_CTRL 16 bit RAM Iface Control Register */
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/* B3_RI_CTRL 16 bit RAM Interface Control Register */
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enum {
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RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
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RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
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@ -613,7 +613,7 @@ enum {
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BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
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BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
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BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
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BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */
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BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
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BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
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BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
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BMU_START = 1<<8, /* Start Rx/Tx Queue */
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@ -636,7 +636,7 @@ enum {
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enum {
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BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
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BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
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BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */
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BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
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};
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/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
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